Interrupt Controller Isolation for Mixed-Security Chip Subsystems
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Solution Overview
Problem
Existing isolation methods between subsystems in autonomous driving systems, such as those based on Hypervisor virtualization and multi-SoC combinations, suffer from incomplete isolation, increased complexity, and high risk of common cause failures, leading to reduced security levels and unreliable communication.
Innovation Solution
A security isolation apparatus and method that integrates subsystems of different security levels within a single chip, utilizing an interrupt controller of higher security level to manage interrupts and authenticate access requests, ensuring physical isolation and secure communication between subsystems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Hypervisor-based virtualization isolation is used, then multiple guest OSs can run on different cores, but common cause failure risk increases due to single point of failure
Solution Approach 1:
The patent segments the processor into multiple independent cores (first core and second core) where each core runs a different guest OS independently. The interrupt controller is physically separated into the first subsystem, creating distinct isolation boundaries that prevent common cause failures while maintaining the ability to run multiple OSs.
Solution Approach 2:
The patent combines multiple subsystems (first subsystem with high security level and second subsystem with low security level) into a single chip architecture. This merging eliminates the need for separate chips and complex inter-chip communication while maintaining security isolation through the interrupt controller design.
2Reliability
If multiple SoCs are combined for isolation, then subsystem isolation is achieved, but device complexity and cost increase
Solution Approach 1:
The patent merges multiple subsystems into a single chip, eliminating the need for separate SoCs and complex main board connections. The first subsystem and second subsystem are integrated within one chip, reducing device complexity while maintaining isolation through the interrupt controller architecture.
Solution Approach 2:
The interrupt controller in the first subsystem serves multiple functions: it manages interrupts for both the first subsystem and the second subsystem, and provides isolation between different security levels. This multi-functionality reduces the need for separate isolation mechanisms and simplifies the overall system.
3Adaptability or versatility
If main SoC communicates with MCU via intermediate communication line, then communication between subsystems is enabled, but transmission speed decreases and reliability reduces
Solution Approach 1:
The patent extracts the communication bottleneck by eliminating the intermediate communication line between separate chips. The first subsystem and second subsystem communicate directly through integrated interfaces within the same chip, removing the transmission delay and reliability issues associated with inter-chip communication.
Data Source
AI summary
A system includes a first subsystem and a second subsystem that are used in a same chip. A security level of a first physical resource included in the first subsystem is higher than a security level of a second physical resource included in the second subsystem. The first subsystem includes an interrupt controller, and the interrupt controller is configured to manage an interrupt of a peripheral of the second subsystem. Embodiments of this application are for isolation between subsystems of different security levels in a chip.