Interrupt Controller Dynamic Routing for Multi-Processor Stability
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Solution Overview
Problem
Current interrupt routing schemes in systems with multiple processors fail to maintain stable performance under critical conditions when processors become busy or unavailable, as they cannot efficiently handle and route multiple interrupt requests simultaneously.
Innovation Solution
An interrupt controller with a receiving circuit and a controlling circuit that dynamically routes interrupt request events to processors based on weighting values, pre-request inquiries, and urgency adjustments, employing time-division arbitration and rate control logic to manage interrupt inputs effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current interrupt routing schemes are used, then simple processor operation is maintained, but system performance and stability deteriorate under critical conditions when processors become busy or unavailable
Solution Approach 1:
The interrupt routing scheme transitions from static to dynamic by continuously monitoring processor availability status and adapting routing decisions in real-time. The system dynamically selects target processors based on current load conditions, ensuring stable performance under varying operational states without requiring complex manual configuration
Solution Approach 2:
The system implements feedback mechanisms by monitoring processor busy/unavailable states and using this information to adjust interrupt routing decisions. The routing controller receives status feedback from processors and modifies routing behavior accordingly, maintaining system stability while avoiding overly complex predetermined routing tables
2Productivity
If interrupt requests are routed to available processors, then system responsiveness improves, but request rejection likelihood increases when all processors are busy
Solution Approach 1:
The system performs preliminary actions by proactively identifying and selecting available processors before interrupt requests arrive. The routing controller maintains an updated view of processor availability and pre-establishes routing paths to suitable processors, enabling rapid response while minimizing rejections through advance preparation
Solution Approach 2:
The interrupt routing controller acts as an intermediary between interrupt sources and processors, intelligently matching requests to appropriate available processors. This mediator function balances load distribution and ensures requests are routed to processors that can handle them, improving both responsiveness and acceptance rates without overwhelming any single processor
3Productivity
If multiple interrupt requests are handled simultaneously, then system throughput increases, but routing accuracy decreases when processors are unavailable
Solution Approach 1:
The system segments interrupt handling by dividing multiple concurrent requests into separate routing decisions, evaluating each request against current processor availability. This segmentation allows high throughput by processing multiple requests in parallel while maintaining routing accuracy through independent evaluation of each request's target processor selection
Data Source
AI summary
An interrupt controller coupled to a plurality of processors is provided to rout at least one interrupt request event to at least one of the processors. The interrupt controller includes a receiving circuit and a controlling circuit. The receiving circuit receives at least one interrupt input, and the controlling circuit, generates the at least one interrupt request event based on the received at least one interrupt input and routes the at least one interrupt request event generated to the at least one of the processors. The plurality of processors including at least a first processor and a second processor, the first and second processors arranged to process interrupt request event(s), and the controlling circuit is arranged to withdraw/cancel assertion of an interrupt request event that has been transmitted to the first processor.