Interrupt Controller Merging Multiple Image Processor Signals

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Solution Overview

Problem

Conventional image forming apparatuses experience time delays and inefficient system performance due to sequential processing of interrupt requests from multiple image processors, leading to prolonged data bus occupation and repetitive operations in checking interrupt routine completions.

Innovation Solution

An image forming apparatus and control method that generate a single interrupt signal only after receiving interrupt requests from multiple image processors, allowing a single interrupt routine to be executed, and utilizing a controller with AND gates and counters to synchronize memory and secondary cache, thereby minimizing time delays and optimizing system performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If interrupt requests from multiple image processors are processed sequentially one at a time, then each interrupt request can be handled in order, but time delay occurs and system performance deteriorates

Engineering Contradiction:

Improvetime delay in processing interrupt requestsVSAvoidsystem performance

Core Design Contradiction:

Loss of timeVSProductivity

Solution Approach 1:

The patent merges multiple interrupt requests from different image processors into a single interrupt request. The interrupt controller combines interrupt signals from multiple sources (e.g., cyan, magenta, yellow, black image processors) into one unified interrupt signal, allowing the CPU to handle all pending interrupts in a single interrupt routine execution rather than processing them sequentially as separate interrupts.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The interrupt controller is designed with multi-functionality to handle various types of interrupt requests from multiple image processors simultaneously. It can receive, combine, and manage interrupts from different color channels and processor types through a universal interrupt interface, enabling a single CPU interrupt routine to serve multiple specialized functions.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If individual interrupt routines are executed for each image processor, then each processor's specific requirements are met, but repetitive checking operations increase device complexity

Engineering Contradiction:

Improveinterrupt request handling accuracyVSAvoidcomplexity of interrupt routine management

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

A single interrupt routine is designed to universally handle interrupt requests from multiple image processors. The routine includes centralized checking logic that can identify and process interrupts from different sources (cyan, magenta, yellow, black processors) without requiring separate checking operations for each processor, thereby reducing complexity while maintaining reliable interrupt handling.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The interrupt controller automatically manages the consolidation and routing of interrupt requests without requiring manual intervention or complex external control. The system self-services by having the interrupt controller autonomously combine interrupts and trigger appropriate CPU responses, reducing the burden on the CPU and simplifying overall system management.

Inventive Principle:

Principle #25Self-service

3Reliability

If the data bus is occupied for extended periods due to sequential interrupt processing, then complete processing of each interrupt is ensured, but processing requests from other devices are delayed

Engineering Contradiction:

Improveinterrupt routine completionVSAvoiddata bus availability

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

Multiple interrupt requests are merged into a single interrupt event, causing the data bus to be occupied for one consolidated interrupt routine execution rather than multiple sequential executions. This reduces the total time the data bus is occupied while ensuring all interrupt requests are processed, thereby improving data bus availability for other devices.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The interrupt controller continuously monitors and consolidates interrupt requests from multiple image processors, ensuring that the CPU responds to all pending interrupts in a continuous manner. This continuous action prevents gaps in interrupt processing while minimizing overall data bus occupation time, maintaining both reliability and speed.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS8171198B2Image forming apparatus and control method thereof

Publication Date: 2012.05.01 HEWLETT PACKARD DEVELOPMENT COMPANY LP

AI summary

An image forming apparatus and a control method thereof. The image forming apparatus includes a plurality of image processors which process an image to be formed on a printing medium corresponding to a plurality of colors, a processor which executes an interrupt routine with respect to the plurality of image processors, and a controller which generates an interrupt signal and transmits the interrupt signal to the processor if at least two the plurality of image processors generate interrupt requests so that the processor executes the interrupt routine.