Interrupt Controller with MMIO Routing Circuitry
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Solution Overview
Problem
Traditional interrupt systems rely on direct line connections, which are limited and inflexible, making it difficult to manage multiple interrupts and identify their sources, leading to complex interrupt controllers with limited feature sets.
Innovation Solution
A Memory Mapped Input/Output (MMIO) based interrupt controller with a set of readable registers that allows multiple entities to send interrupts to a common target, using routing circuitry to persistently store and route interrupt messages, enabling flexible feature support and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If direct line connections are used for interrupts, then interrupt delivery is simple and reliable, but the system becomes inflexible and difficult to scale for multiple interrupt sources
Solution Approach 1:
The patent introduces an interrupt controller as an intermediary device that mediates between multiple interrupt sources and processor cores. The controller receives interrupt requests from various sources, stores interrupt cause information in registers, and manages interrupt delivery to appropriate processor cores, thereby enabling flexible interrupt management without requiring direct connections between each interrupt source and processor.
Solution Approach 2:
The interrupt controller is designed as a universal device that can handle multiple types of interrupt sources (both direct line connections and MMIO-based interrupts) and serve multiple processor cores. The controller provides a unified interface for interrupt management that works across different interrupt types and targets, making the system adaptable to various configurations without requiring separate dedicated controllers for each interrupt source.
2Adaptability or versatility
If MMIO-based interrupt routing is implemented, then flexibility and scalability are improved, but the need for persistent storage of interrupt data increases device complexity
Solution Approach 1:
The interrupt controller is segmented into distinct functional components: MMIO interface circuitry for receiving memory-mapped interrupt requests, routing circuitry for directing interrupts to appropriate targets, and a set of readable registers for storing interrupt cause information. This segmentation allows each component to be optimized independently, managing complexity through modular design while maintaining flexibility in handling different interrupt sources.
3Productivity
If multiple entities send interrupts to a common target, then resource utilization is improved, but identifying the interrupt source becomes more difficult
Solution Approach 1:
The interrupt controller implements feedback by storing interrupt cause information in readable registers that provide information back to the processor core about the interrupt source. When an interrupt is delivered to a common target, the target can read the interrupt cause register to identify which entity generated the interrupt, enabling efficient interrupt handling while maintaining source identification capability through this feedback mechanism.
Data Source
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AI summary
An interrupt controller includes a fabric slave that can receive MMIO operation requests, a plurality of output interrupt lines, a plurality of interrupt registers with each interrupt register corresponding to an output interrupt line, a MMIO routing circuit in communication with the fabric slave and the interrupt registers, a plurality of input interrupt lines for receiving line interrupts, and a line interrupt routing circuit in communication with the input interrupt lines and the interrupt registers. The interrupt registers store data for an interrupt that serves as an indication of the source of the interrupt and/or what task(s) need to be done for the interrupt.