Interrupt Controller Scheduling for Processor Core Stalling

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Solution Overview

Problem

Network processors face challenges in handling interrupts during critical operations, as they may stall other processor cores until the interrupt is handled, and disabling or prioritizing interrupts is not always effective in ensuring timely processing.

Innovation Solution

Converting interrupts into scheduled events by using an interrupt controller that prioritizes and schedules them, utilizing a vector table and scheduler engine to manage interrupt status and work properties, and storing interrupt work properties in main memory to optimize resource utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If interrupts are disabled or only highest priority interrupts are accepted during critical operations, then processor core stalling is reduced, but interrupt handling timeliness cannot be guaranteed

Engineering Contradiction:

Improveprocessor core throughputVSAvoidinterrupt handling timeliness

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The interrupt handling process is segmented into two distinct paths: critical interrupts that require immediate processing and non-critical interrupts that can be deferred to scheduled events. This segmentation allows the system to maintain high processor throughput during critical operations while ensuring that important interrupts are still handled timely through the immediate processing path.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system performs preliminary classification of interrupts at the point of reception, determining whether each interrupt requires immediate processing or can be scheduled. This preliminary action prevents processor stalling by pre-identifying which interrupts can be deferred, while maintaining reliability by ensuring critical interrupts are immediately processed.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If interrupts are immediately processed, then interrupt handling timeliness is ensured, but processor core stalling occurs during critical operations

Engineering Contradiction:

Improveinterrupt handling timelinessVSAvoidprocessor core throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The system dynamically adjusts interrupt handling behavior based on the current operational state of the processor. During critical operations, the system dynamically switches to a more selective interrupt handling mode that defers non-critical interrupts to scheduled events, while maintaining immediate processing for critical interrupts. This dynamic adaptation resolves the contradiction by allowing the system to optimize for timeliness when necessary and for throughput when safe to do so.

Inventive Principle:

Principle #15Dynamics

3Productivity

If interrupts are converted to scheduled events, then resource utilization is optimized, but interrupt handling may be delayed

Engineering Contradiction:

Improveresource utilizationVSAvoidinterrupt handling delay

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The system applies different quality levels of interrupt handling based on the specific interrupt type and system state. Critical interrupts receive immediate local processing with high priority, while non-critical interrupts are converted to scheduled events with lower priority. This local quality differentiation optimizes resource utilization for non-critical interrupts while minimizing delays for critical interrupts, resolving the contradiction between resource efficiency and timing.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS9665508B2Method and an apparatus for converting interrupts into scheduled events

Publication Date: 2017.05.30 MARVELL ASIA PTE LTD

AI summary

A method and an apparatus embodying the method for converting interrupts into scheduled events, comprising receiving an interrupt at an interrupt controller; determining a vector number for the interrupt; determining properties of an interrupt work in accordance with the vector number; and scheduling the interrupt work in accordance with the properties of the interrupt work, is disclosed.