Interrupt Controller Using Shared Memory for Scalable Signalling
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Solution Overview
Problem
Existing interrupt controllers face challenges in scalability and design complexity due to the need for dedicated interrupt buses and protocols, which become cumbersome as the number of processors and interrupts increases.
Innovation Solution
Utilize a cache coherent interconnect to distribute interrupts by storing interrupt tracking structures in shared memory and managing coherency using existing cache coherency protocols, eliminating the need for dedicated interrupt buses and allowing scalability through memory-based structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If dedicated interrupt buses and protocols are used, then interrupt distribution is achieved, but design complexity and scalability are worsened as the number of processors and interrupts increases
Solution Approach 1:
The patent applies universality by making the cache coherent interconnect serve dual purposes: both memory access and interrupt distribution. Instead of having separate dedicated interrupt buses, the existing interconnect infrastructure is reused to carry interrupt tracking structure updates, eliminating the need for specialized interrupt communication hardware and reducing overall system complexity while maintaining scalability
Solution Approach 2:
The patent merges the interrupt distribution function with the memory access infrastructure. By combining interrupt signalling with cache coherent memory operations, the system eliminates separate interrupt buses and protocols, reducing design complexity while allowing the unified infrastructure to scale with the number of processors and interrupts
2Adaptability or versatility
If cache coherent interconnect is used for interrupt distribution, then scalability is improved, but coherency management complexity increases
Solution Approach 1:
The patent applies self-service by leveraging the cache coherent interconnect's existing coherency protocols to automatically manage consistency of interrupt tracking structures across multiple processors. The hardware itself handles the coherency maintenance through standard cache coherence mechanisms, eliminating the need for additional software management or complex control logic, thus achieving scalability without proportionally increasing coherency management complexity
Data Source
AI summary
An interrupt controller controls signalling of a given interrupt having a given interrupt identifier to a target interrupt handling context, by controlling one or more memory write requests to be issued in accordance with a coherency protocol supported by a cache coherent interconnect, to maintain a set of memory-based interrupt tracking structures corresponding to the target interrupt handling context, including: a selected interrupt queue structure selected from among a plurality of interrupt queue structures based on the given interrupt identifier, to queue the given interrupt for processing by the target interrupt handling context; and a queue status summary structure to indicate which of the plurality of interrupt queue structures hold pending interrupts awaiting processing by the target interrupt handling context.