Intelligent Interrupt Distributor for Power-Efficient Multi-Core Systems
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Solution Overview
Problem
Microcontroller systems face challenges in balancing throughput and power consumption, particularly when handling multiple interrupts simultaneously, as existing techniques to minimize power dissipation often compromise system performance.
Innovation Solution
A multi-processor system architecture with an Intelligent Interrupt Distributer (IID) that manages operating voltage and frequency, distributing interrupts among processors to maintain throughput while reducing power consumption, allowing for configuration between throughput optimization and power reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the operating voltage and frequency are reduced to minimize power consumption, then power dissipation is reduced, but system throughput deteriorates
Solution Approach 1:
The system is divided into multiple processor cores (at least two cores) that share the interrupt handling workload. Each core can independently handle interrupts, allowing the system to maintain throughput while operating at lower voltage and frequency. The interrupt distributor allocates interrupts to available cores, ensuring that power consumption is reduced without sacrificing overall system performance.
2Productivity
If more processors are added to compensate for throughput loss from reduced voltage, then throughput is maintained, but device complexity increases
Solution Approach 1:
An interrupt distributor component is introduced as an intermediary between peripheral devices and multiple processor cores. This distributor manages the complexity of interrupt allocation by receiving interrupts from peripherals and intelligently distributing them to available processor cores. This mediation layer simplifies the overall system architecture compared to having each core directly connected to all peripherals, while still enabling throughput maintenance through parallel processing.
3Loss of energy
If techniques such as body biasing and clock gating are used to reduce power consumption, then power dissipation is minimized, but interrupt handling capability deteriorates
Solution Approach 1:
The system dynamically adjusts the operational state of multiple processor cores based on interrupt workload and power requirements. The interrupt distributor monitors core availability and allocates interrupts dynamically, allowing the system to maintain interrupt handling capability while cores can be placed in low-power states when not actively processing interrupts. This dynamic allocation ensures that interrupt handling reliability is maintained even when power consumption is minimized through techniques like clock gating.
Data Source
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AI summary
An intelligent interrupt distributor balances interrupts (workload) in a highly parallelized system. The intelligent interrupt distributor distributes the interrupts between the processor cores. This allows lowering of voltage and frequency of individual processors and ensures that the overall system power consumption is reduced.