Interrupt Handling Apparatus for Equal-Model Processor Latency Management
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Solution Overview
Problem
Equal-model processors face challenges in efficiently handling interrupts due to potential erroneous execution when interrupts are processed during instruction scheduling, leading to delayed interrupt processing and performance deterioration, as they require complex algorithms and are limited to specific instruction types.
Innovation Solution
An interrupt support determining apparatus and method that compares current latency with remaining latency, updating the remaining latency and determining if interrupt processing is allowed based on this comparison, allowing interrupts to be processed only when the remaining latency is equal to or less than 1, thereby preventing erroneous execution and improving processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If interrupt processing is allowed during instruction execution in an equal-model processor, then interrupt response speed is improved, but erroneous execution may occur due to latency mismatches
Solution Approach 1:
The patent applies preliminary action by checking whether the current instruction type and remaining latency satisfy predetermined conditions before allowing interrupt processing. This pre-check mechanism prevents erroneous execution by ensuring that interrupts are only processed when it is safe to do so, while still maintaining fast interrupt response when conditions are met.
2Reliability
If interrupt processing is restricted to specific instruction types, then execution correctness is maintained, but interrupt processing frequency is reduced
Solution Approach 1:
The patent changes the parameter for determining interrupt eligibility from solely instruction type to a combination of instruction type and remaining latency. By introducing remaining latency as an additional parameter, the system can process interrupts more frequently across different instruction types while maintaining execution correctness through the predetermined condition check.
3Reliability
If a complex algorithm is used to prevent erroneous execution during interrupt handling, then execution correctness is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by implementing a simple yet targeted check that specifically evaluates whether the current instruction type and remaining latency satisfy predetermined conditions. This localized check focuses only on the critical parameters needed to prevent erroneous execution, avoiding the need for complex global algorithms while maintaining execution correctness.
Data Source
AI summary
An interrupt support determining apparatus and method for an equal-model processor, and a processor including the interrupt support determining apparatus are provided. The interrupt support determining apparatus determines whether an instruction input to a processor decoder is a multiple latency instruction, compares a current latency of the instruction with a remaining latency if the instruction is a multiple latency instruction, and updates the current latency to the remaining latency if the current latency is greater than the remaining latency.