Interrupt Handling for Shared Network Packets

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Solution Overview

Problem

In shared network adapter environments, efficiently managing interrupts to a host operating system is challenging, particularly when handling large data transfers, as it can lead to excessive CPU usage and power consumption.

Innovation Solution

A method and system where a shared network adapter identifies data to be processed by a host, stores it in receive (RX) data queues, sets a bitmask to indicate which queues contain data, checks the interrupt state of the host, and determines whether to transmit an interrupt based on this state, thereby optimizing interrupt transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If interrupts are transmitted for every received data packet, then the host is promptly notified of data availability, but CPU usage and power consumption increase excessively

Engineering Contradiction:
ImproveData notification speedVSAvoidCPU usage and power consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent combines multiple interrupt notifications into a single interrupt by using an interrupt status register that aggregates the state of multiple RX data queues. Instead of generating separate interrupts for each queue or packet, the system merges the interrupt signals and sends a unified interrupt to the host when any queue has data available, thereby reducing CPU overhead and power consumption while maintaining timely notification.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The interrupt status register serves multiple functions: it tracks the state of multiple RX data queues simultaneously, consolidates interrupt conditions from different queues, and provides a single notification mechanism for the host. This multi-functional approach eliminates the need for separate interrupt handling logic for each queue, reducing overall system complexity and resource usage.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If multiple RX data queues are used to facilitate data transfer, then data organization and processing efficiency improve, but interrupt management complexity increases

Engineering Contradiction:
ImproveData transfer efficiencyVSAvoidInterrupt management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The interrupt status register is designed to universally monitor all RX data queues through a single register, with each bit corresponding to a specific queue's interrupt status. This universal monitoring mechanism simplifies interrupt management by providing a unified view of all queue states, eliminating the need for complex individual queue management logic while maintaining the benefits of multiple queues for data organization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent uses bitmask representation where each bit in the interrupt status register acts as a visual indicator (like a color change) for the state of corresponding RX data queues. A set bit indicates that a queue has data ready, providing a clear, easily detectable state that simplifies interrupt handling logic. This binary state representation makes it straightforward to determine which queues require attention without complex management overhead.

Inventive Principle:
Principle #32Color changes

Data Source

PatentUS20250168123A1Interrupt handling for received network packets
Publication Date: 2025.05.22 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US20250168123A1 patent drawing
  • US20250168123A1 patent drawing
  • US20250168123A1 patent drawing

AI summary

Embodiments herein describe techniques for providing interrupts from a shared network adapter to a host operating system or control program. A register can store an interrupt state of the host that indicates whether an interrupt is required. For example, the host may still be busy processed previous received data (e.g., a packet received from a network), which means no interrupt is required. When the host has processed each of the requests from the shared network adapter, the interrupt state in the register can be changed that if any additional data is received, an interrupt is required. Moreover, the register can include a bitmask to indicate which of a plurality of receive data queues has data ready for the host to process.