Interrupt Edge-Detect Latching Register Across Asynchronous Clock Domains
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Solution Overview
Problem
Existing methods for transferring interrupts across asynchronous clock domains in digital systems require additional processor time and power due to the need for synchronization, which can lead to lost interrupt indications and inefficiencies.
Innovation Solution
A controller responsive to one clock domain generates a control signal pulse that is synchronized to the target domain's clock, allowing immediate feedback of read data to clear interrupt register bits only if they were logically one, eliminating the need for a write-back operation and reducing synchronization delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a register in the peripheral domain receives interrupt signals and the processor writes back the read value through synchronization to clear bits, then interrupt detection reliability is improved, but processor time and power consumption increase
Solution Approach 1:
The patent applies preliminary action by pre-synchronizing the interrupt register write-back operation to the processor clock domain before the actual interrupt handling occurs. The synchronization logic prepares the cleared register value in advance, so when the processor performs the write-back, the data is already aligned with the processor clock domain, eliminating the need for additional synchronization delays and reducing processor time consumption.
Solution Approach 2:
The patent introduces an intermediary synchronization mechanism that acts as a buffer between the peripheral domain interrupt register and the processor domain. This intermediary structure holds and transfers the cleared register value through synchronized clock domains, ensuring reliable interrupt detection while managing the timing differences between domains without requiring the processor to wait for synchronization operations.
2Reliability
If a register in the peripheral domain receives interrupt signals and the processor writes back the read value through synchronization to clear bits, then interrupt detection reliability is improved, but power consumption increases
Solution Approach 1:
The synchronization of the interrupt register write-back value is performed in advance in the peripheral domain before transfer to the processor domain. This preliminary synchronization ensures that the data is ready when needed, reducing the need for repeated or extended synchronization operations that would consume additional power during processor execution.
Solution Approach 2:
The intermediary synchronization mechanism efficiently manages data transfer between clock domains by performing the synchronization operation once in the peripheral domain and then transferring the pre-synchronized value to the processor domain. This approach reduces the total number of synchronization operations required, thereby reducing overall power consumption while maintaining interrupt detection reliability.
3Reliability
If traditional synchronization methods are used to transfer interrupts across clock domains, then data transfer reliability is improved, but the system requires additional processor time and power for write-back operations
Solution Approach 1:
The patent employs an intermediary synchronization mechanism that acts as a bridge between the peripheral domain interrupt register and the processor domain. This intermediary structure handles the complexity of cross-clock-domain synchronization automatically, maintaining data transfer reliability while shielding the processor from the operational complexity of synchronization management.
Solution Approach 2:
The synchronization mechanism is designed to operate autonomously in the peripheral domain, automatically synchronizing and transferring the interrupt register write-back value to the processor domain without requiring processor intervention. This self-service approach reduces operation complexity from the processor's perspective while maintaining reliable data transfer across clock domains.
Data Source
AI summary
A digital circuit may have at least two asynchronous clock domains with a controller responsive to a first domain clock signal and a target responsive to a second domain clock signal. A first domain control signal pulse is generated in response to the first domain clock signal for controlling the target. Each assertion the first domain control signal pulse is detected and used to form a second domain control signal pulse synchronized to the second domain clock signal. The target is controlled using the second domain control signal pulse. If the target is a clear-on-read register, contents of the clear-on-read register are latched in a feedback register in response to the first domain control signal pulse and provided to the controller. Each bit of the clear-on-read register is reset in response to the second domain control signal pulse only if the corresponding latched content of each bit in the feedback register is a logical one.