Interrupt Latency Measurement Using Timestamp Registers

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Solution Overview

Problem

Existing interrupt processing systems lack a reliable method to measure and manage interrupt latency effectively, which can lead to inefficiencies in handling high-priority events, especially in systems with asynchronous hardware interrupts.

Innovation Solution

The implementation of up counters and time stamp registers to quantify and communicate interrupt latency, allowing interrupt service routines to determine elapsed time and set thresholds for responsive handling, with options for generating non-maskeable interrupts or abandoning requests if latency exceeds a predetermined threshold.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If interrupt latency measurement and management mechanisms are implemented, then system responsiveness and reliability are improved, but device complexity increases

Engineering Contradiction:
Improveinterrupt handling reliabilityVSAvoidinterrupt processing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces intermediary components (up counters, time stamp registers, and latency calculation logic) that mediate between the interrupt request and the interrupt service routine. These intermediaries measure latency without requiring fundamental changes to the interrupt processing architecture, thus improving reliability while adding controlled complexity through dedicated measurement components.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The interrupt processing system performs self-measurement of its own latency characteristics. The up counters and time stamp registers automatically track timing information during interrupt processing, and the system itself uses this information to manage latency, eliminating the need for external measurement apparatus and reducing overall system complexity.

Inventive Principle:
Principle #25Self-service

2Productivity

If latency threshold mechanisms are implemented to abandon requests, then system efficiency is improved, but loss of information increases

Engineering Contradiction:
Improveinterrupt handling efficiencyVSAvoidinterrupt request information
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

The patent implements feedback mechanisms where latency measurements are continuously monitored and compared against predetermined thresholds. When thresholds are exceeded, the system provides feedback to abandon the interrupt request. This feedback loop enables efficient latency management while maintaining information integrity through controlled decision-making based on measured conditions rather than arbitrary abandonment.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9715468B2Method of providing timing information for interrupts
Publication Date: 2017.07.25 TEXAS INSTRUMENTS INC
  • US9715468B2 patent drawing
  • US9715468B2 patent drawing
  • US9715468B2 patent drawing

AI summary

It is desirable for interrupt handling routines to be aware of the interrupt latency—the time between a interrupt request is received and the time when the interrupt service routine begins executing. A method is shown wherein the latency is measured by a dedicated counter and is available to the interrupt service routine. Alternately, a threshold may be set indicating the maximum acceptable latency and the interrupt service routine is signaled when said maximum is reached.