Interrupt Mask Bit for Software Thread Blocking Prevention
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Solution Overview
Problem
Software threads are often blocked due to processing external device interrupts, which can lead to negative consequences such as network packet drops or slowdowns, especially in real-time processing applications like stock trading software, as they are suspended while the CPU handles hardware interrupts.
Innovation Solution
A method that involves setting an interrupt mask bit for a software thread to prevent it from being interrupted by external device interrupts, allowing it to be redirected to another CPU if the target CPU is busy processing interrupts, using an associated interrupt avoidance variable to dynamically control interrupt handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CPU processes hardware interrupts normally, then external devices can be responded to timely, but software threads may be blocked and suspended
Solution Approach 1:
The patent segments the interrupt handling process by introducing an interrupt mask bit that divides CPU operation into interruptible and non-interruptible periods. During critical software thread execution, the interrupt mask bit is set to prevent interrupt handling, separating the timing of thread execution from interrupt processing. This allows the system to prioritize thread continuity while maintaining the capability to handle interrupts when appropriate.
Solution Approach 2:
The patent applies preliminary action by setting the interrupt mask bit before executing critical software threads. This preemptive measure ensures that interrupts cannot block the thread during execution. The interrupt mask bit is configured in advance based on the interrupt avoidance variable, preventing potential thread blocking before it can occur.
2Productivity
If the interrupt mask bit is set to prevent thread blocking, then software thread execution is uninterrupted, but interrupt processing may be delayed
Solution Approach 1:
The patent implements dynamic control of the interrupt mask bit based on the interrupt avoidance variable and system conditions. The interrupt mask bit is not permanently set but is dynamically adjusted - enabled when software threads require uninterrupted execution and disabled when interrupt processing is needed. This dynamic approach balances thread execution speed with interrupt processing timeliness.
Solution Approach 2:
The patent changes the state parameter of the interrupt mask bit (from cleared to set, and vice versa) based on the interrupt avoidance variable. When the interrupt avoidance variable indicates a thread should not be blocked, the interrupt mask bit parameter is changed to the set state, preventing interrupts. When interrupt processing is needed, the parameter is changed back to the cleared state, allowing normal interrupt handling.
3Productivity
If interrupts are redirected to another CPU, then the original CPU can continue thread execution, but interrupt redirection complexity increases
Solution Approach 1:
The patent uses the interrupt mask bit as an intermediary mechanism between software threads and hardware interrupts. Rather than implementing complex interrupt redirection logic, the interrupt mask bit serves as a simple binary mediator that either allows or blocks interrupts on a given CPU. This intermediary approach simplifies the system by providing a straightforward control mechanism without requiring sophisticated interrupt redistribution algorithms.
Data Source
AI summary
According to one exemplary embodiment, a method for preventing a software thread from being blocked due to processing an external device interrupt is provided. The method may include receiving the software thread, whereby the software thread has an associated interrupt avoidance variable. The method may also include determining a processor to receive the software thread. The method may then include sending the software thread to the determined processor. The method may further include setting an interrupt mask bit associated with the processor based on the interrupt avoidance variable. The method may also include receiving the external device interrupt. The method may then include redirecting the received external device interrupt to a second processor, whereby the redirecting is based on the interrupt mask bit.