Interrupt-Driven Memory Address Mapping for Secure MMIO Scaling
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Solution Overview
Problem
Existing memory mapped input/output (MMIO) technologies face issues of large resource consumption and security vulnerabilities due to increased address mapping range as the number of memory devices or memory size grows, leading to inefficiencies and potential security risks.
Innovation Solution
A memory device with an address translator that dynamically maps physical addresses to device addresses in response to interrupts, allowing for efficient conversion of traffic across different memory regions using a local processor and interrupt controller, minimizing the size of the address register and preventing excessive resource consumption and security issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If MMIO is used with all memory spaces open to the outside, then memory devices can access each other's memory, but the range of addresses to be mapped increases leading to large resource consumption and security vulnerabilities
Solution Approach 1:
The patent segments the memory address space into multiple regions, each with different access permissions. Instead of opening all memory spaces to the outside, the system divides memory into accessible regions and non-accessible regions, allowing selective access control. This reduces the overall address mapping range that needs to be managed while maintaining necessary memory access capabilities between devices.
Solution Approach 2:
The patent applies different access permissions to different memory regions. Each memory region can have its own access control settings, allowing the system to open only specific regions to external access while keeping other regions private. This local differentiation reduces the total address mapping range required while maintaining adaptability for specific access needs.
2Adaptability or versatility
If the range of addresses to be mapped increases, then more memory devices and larger memory sizes can be accessed, but resource consumption increases
Solution Approach 1:
The patent implements dynamic address mapping where the address translation table is updated based on actual access needs. Instead of pre-configuring all possible address mappings, the system dynamically creates or updates mappings only when memory devices need to access specific regions. This reduces resource consumption by maintaining smaller address mapping ranges while preserving the ability to access multiple memory devices and large memory sizes when needed.
Solution Approach 2:
The patent changes the parameters of address mapping dynamically based on system conditions. The address translation table entries can be modified, added, or removed according to actual memory access requirements, allowing the system to optimize resource consumption while maintaining adaptability for different memory device configurations and sizes.
3Adaptability or versatility
If the range of addresses to be mapped increases, then more memory devices and larger memory sizes can be accessed, but security vulnerabilities increase
Solution Approach 1:
The patent segments memory address space into multiple regions with different access control permissions. By dividing memory into accessible and non-accessible regions, the system limits the address mapping range that is exposed to external devices, thereby reducing security vulnerabilities while maintaining necessary memory access capabilities through selective region access.
Solution Approach 2:
The patent applies different security permissions to different memory regions locally. Each region can have its own access control settings, allowing the system to open only specific regions to external access while keeping other regions private and secure. This reduces security vulnerabilities by minimizing the exposed address mapping range while preserving adaptability for authorized access.
Data Source
AI summary
Provided are a memory device and a method for dynamically mapping address thereof, in which the memory device includes a memory including a plurality of memory regions, an address register in which at least one of a memory device different from the memory device or a host stores a device address for accessing the memory, and an address translator configured to receive a first interrupt, and in response to the first interrupt, convert a physical address of the memory mapped to the device address.