Interrupt Controller Priority Register Mapping for Secure Legacy Compatibility
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Solution Overview
Problem
As data processing systems evolve and become more complex, maintaining backwards compatibility with legacy interrupt controllers while allowing advanced interrupt controllers to support new functionality is a challenge, particularly in ensuring secure and predictable interrupt prioritization across different operating systems.
Innovation Solution
A unified set of priority registers with a priority register accessing circuit that provides multiple mappings for priority values, allowing separate control by different priority value managers, including secure and non-secure operating systems, to manage interrupt prioritization while ensuring security and compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a unified set of priority registers is used to store priority values, then backwards compatibility with legacy systems is maintained, but it becomes difficult to support multiple operating systems with different priority value mappings simultaneously
Solution Approach 1:
The priority register accessing circuit is segmented into multiple access interfaces, each with its own mapping configuration. This allows different operating systems to access the same physical priority registers through different mapping relationships, enabling legacy systems and new systems to coexist without interference
Solution Approach 2:
The priority register accessing circuit acts as an intermediary layer between multiple priority value managers and the unified priority registers. It translates different mapping requirements from various operating systems into unified access to the same priority registers, resolving the conflict between compatibility and multi-system support
2Measurement precision
If separate priority registers are provided for each interrupt signal to allow fine-grained control, then interrupt prioritization precision is improved, but the device complexity and resource requirements increase significantly
Solution Approach 1:
A unified set of priority registers is designed to serve multiple operating systems simultaneously with different mapping configurations. The same physical registers provide fine-grained control for legacy systems while also supporting new systems with extended priority values, eliminating the need for separate register sets
3Adaptability or versatility
If legacy operating systems continue to use traditional priority value mappings, then compatibility is maintained, but secure peripherals may be interrupted by non-secure interrupts which is a security risk
Solution Approach 1:
The priority register accessing circuit serves as a security intermediary that translates legacy operating system access requests into secure priority value assignments. It ensures that legacy systems can use traditional mappings while secure peripherals are automatically assigned higher priority values, preventing security vulnerabilities
Data Source
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AI summary
An interrupt controller (2) is provided with priority registers (6) storing priority values P0-P9 used to determine prioritisation between received interrupt signals I0-I9. A priority value accessing circuit (10) provides multiple mappings to the priority values stored in dependence upon the priority value manager (16, 18), seeking to make an access. In this way, a first priority value manager (18), such as a secure operating system, can be given exclusive access to the highest priority values whilst a second priority value manager (16), such as a non-secure operating system, can be given access to a range of priority values as stored which are of a lower priority and yet as written or read by the non-secure operating system appear to the non-secure operating system to have a different, such as higher, priority level.