Hardware Interrupt Controller Context-Sensitive Priority Switching

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Solution Overview

Problem

Conventional interrupt controllers rely on software to manage interrupt prioritization, leading to increased latency and complexity due to the need for frequent changes in priority levels when the system mode or context changes.

Innovation Solution

A hardware-based interrupt controller with multiple interrupt priority registers allows for context-sensitive prioritization, enabling automatic switching of interrupt priority levels based on system mode or context changes without software intervention, using a priority encoder to generate interrupt request signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If software-controlled interrupt prioritization is used, then interrupt priority levels can be dynamically adjusted, but latency increases and system complexity increases due to frequent software intervention

Engineering Contradiction:

Improveinterrupt priority adjustmentVSAvoidinterrupt latency

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent replaces the software-controlled interrupt prioritization mechanism with a hardware-based system. Multiple interrupt priority registers (R0-R3) are implemented in hardware, with a priority selector that automatically chooses the appropriate register based on the current context (sleep mode vs. active mode). This hardware substitution eliminates the latency associated with software intervention while maintaining dynamic adaptability of interrupt priorities.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent implements dynamic interrupt priority management through hardware by providing multiple priority registers that can be selectively activated. The priority selector dynamically switches between different priority registers based on system context, enabling adaptive interrupt prioritization without software intervention. This dynamic hardware switching resolves the contradiction by providing both adaptability and low latency.

Inventive Principle:

Principle #15Dynamics

2Adaptability or versatility

If software routines are used to manage interrupt priorities, then priority levels can be changed, but device complexity increases due to additional programming requirements

Engineering Contradiction:

Improvepriority level controlVSAvoidprogramming complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent replaces software-based priority management with a hardware implementation featuring multiple priority registers (R0-R3) and a priority selector circuit. This hardware system automatically manages interrupt priorities based on system context without requiring software routines or programming changes, thereby reducing device complexity while maintaining adaptability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The hardware-based priority selection system operates autonomously, automatically selecting the appropriate priority register based on the current system context (sleep or active mode). This self-service mechanism eliminates the need for software intervention and reduces programming complexity, as the system manages its own interrupt priorities without external control.

Inventive Principle:

Principle #25Self-service

3Loss of time

If hardware-based interrupt control is used, then latency is reduced, but adaptability decreases when context changes require priority switching

Engineering Contradiction:

Improveinterrupt latencyVSAvoidcontext-sensitive prioritization

Core Design Contradiction:

Loss of timeVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic adaptability in hardware through multiple interrupt priority registers (R0-R3) that can be selectively activated. The priority selector circuit dynamically switches between these registers based on system context (sleep mode using R0, active mode using R1-R3), providing both low latency hardware control and context-sensitive adaptability simultaneously.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent segments the interrupt priority control into multiple dedicated registers (R0 for sleep mode, R1-R3 for active modes) rather than using a single unified register. This segmentation allows the hardware system to quickly switch between different priority configurations based on context, maintaining both low latency and high adaptability through specialized hardware structures.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS7793025B2Hardware managed context sensitive interrupt priority level control

Publication Date: 2010.09.07 VLSI TECHNOLOGY LLC

AI summary

A flexible interrupt controller circuit and methodology are provided which use an interrupt circuit (300) that multiplexes (324) a plurality of interrupt priority registers (321, 322) based on the current context of the system that is identified in mode control selector (326). By using the mode control selector (326) to selectively couple different priority level assignments to a priority encoding module (330), context sensitive switching of the priority levels assigned to each interrupt request can be implemented with reduced latency. The context switch could be based on an OS context ID, power management modes, security modes, and other system defined modes where priority levels would differ. The selected priority level information is used to provide an interrupt request signal (332) which will cause an interrupt to occur in the data processing system.