Interrupt Proxy Unit for SoC Interrupt Processing
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Solution Overview
Problem
In system on chip (SoC) technology, the varying processing times of interrupt tasks across different intellectual properties (IPs) can lead to performance deterioration and errors, especially when user software malfunctions, and the complexity of system structures increases waiting times and the risk of delayed interrupt service routines.
Innovation Solution
The implementation of an interrupt proxy processing unit that stores interrupt status information, processes interrupts in a standardized manner, and releases interrupts independently of the processor, allowing for uniform task processing times and preventing reentry into interrupt service routines, thereby enhancing performance and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the processor core directly processes all interrupt signals from multiple IPs, then the system can handle interrupts, but the processing time varies depending on IP complexity causing performance deterioration
Solution Approach 1:
The interrupt processing function is segmented by introducing an interrupt controller that separates interrupt collection from interrupt processing. The interrupt controller handles all interrupt signals from multiple IPs uniformly, while the processor core only handles the standardized interrupt processing, eliminating time variation caused by direct IP access.
Solution Approach 2:
An interrupt controller is introduced as an intermediary between the IPs and the processor core. This intermediary standardizes the interrupt interface and processing time, allowing the processor core to maintain consistent processing speed regardless of IP complexity.
2Adaptability or versatility
If the system structure is complicated due to increase of IPs, then more functions are available, but waiting time increases due to processor access delay
Solution Approach 1:
The interrupt controller serves as an intermediary that manages communication between multiple IPs and the processor core. It consolidates interrupt signals and standardizes access protocols, reducing waiting time caused by complex system structure while maintaining full functionality.
Solution Approach 2:
The interrupt controller provides a universal interface for all IPs, enabling the processor core to access any IP through a standardized mechanism. This multi-functional controller eliminates the need for processor core to directly manage each IP's specific access protocols.
3Adaptability or versatility
If user software processes interrupt tasks with different execution times, then specific IP requirements are met, but system errors occur due to timing differences
Solution Approach 1:
The system is segmented into an interrupt controller that handles timing-critical operations and user software that handles business logic. This separation ensures that timing differences in user software processing do not affect system reliability, as the interrupt controller maintains uniform timing for all IPs.
Solution Approach 2:
The interrupt controller acts as an intermediary that isolates timing variations between different IP processing paths. It ensures that all interrupt signals are processed with uniform timing regardless of the specific IP or user software involved, preventing system errors.
4Ease of operation
If the processor core directly accesses each IP for interrupt processing, then interrupt handling is straightforward, but reentry errors occur when high-speed processor repeats interrupt service routine
Solution Approach 1:
The interrupt controller serves as an intermediary that manages the interrupt service routine execution. It prevents the processor core from directly accessing each IP and repeating interrupt service routines, thereby eliminating reentry errors while maintaining simple interrupt handling through standardized interfaces.
Data Source
AI summary
Provided is a system on chip (SoC) capable of rapidly processing interrupts generated in various modules without causing an error. The SoC includes a processor configured to process a task, a plurality of modules on the SoC and operationally coupled to the processor through a system bus, and an interrupt proxy processing unit operationally coupled to the processor and the plurality of modules and configured to solely process an interrupt-related task from a first module of the plurality of modules.