Dual-Core Interrupt Redirection for Execution Drift Control

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Solution Overview

Problem

Computing systems used in automotive and industrial IoT applications face challenges in mitigating execution drift, which can lead to safety issues due to asynchronous events causing processor cores to lag behind each other.

Innovation Solution

The system dynamically redirects asynchronous events to leading processor cores, allowing for the reduction and control of execution drift without allocating dedicated CPU cores for interrupt handling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If asynchronous events are handled by any available processor core, then system responsiveness is maintained, but execution drift between processor cores increases

Engineering Contradiction:
Improvesystem responsivenessVSAvoidexecution drift control
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The system continuously monitors execution drift between processor cores and uses this feedback to dynamically adjust interrupt redirection policies. The drift detection mechanism compares execution states of paired cores and redirects asynchronous events to the lagging core when drift exceeds thresholds, creating a closed-loop control system that maintains synchronization while preserving responsiveness.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The interrupt redirection policy is made dynamic rather than static. The system adapts interrupt routing decisions based on real-time execution drift conditions, switching between different redirection strategies (redirect to leading core, redirect to lagging core, or maintain original routing) depending on the current synchronization state of processor cores.

Inventive Principle:
Principle #15Dynamics

2Reliability

If dedicated CPU cores are allocated for interrupt handling, then execution drift is reduced, but system cost and resource utilization increase

Engineering Contradiction:
Improveexecution drift controlVSAvoidsystem cost
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Processor cores are designed to serve multiple functions - they can execute safety-critical workload pairs during normal operation and simultaneously handle asynchronous events when needed. The system dynamically assigns roles to cores based on execution drift conditions, allowing any core to temporarily take on interrupt handling responsibilities without requiring dedicated interrupt处理器.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system uses its own processor cores to handle interrupts rather than requiring separate dedicated hardware. By redirecting asynchronous events to available cores based on drift conditions, the system serves its own synchronization needs using existing computational resources, eliminating the need for additional dedicated interrupt handling hardware.

Inventive Principle:
Principle #25Self-service

3Productivity

If processor cores execute workload pairs independently, then processing throughput is maximized, but diagnostic coverage decreases

Engineering Contradiction:
Improveprocessing throughputVSAvoiddiagnostic coverage
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system introduces an intermediary comparison mechanism that periodically evaluates corresponding variables from independently executing workload pairs. This mediator function detects mismatches between cores while allowing independent execution to continue, providing diagnostic coverage without significantly impacting processing throughput since comparisons occur at controlled intervals rather than continuously.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3885913B1Computing system for mitigating execution drift
Publication Date: 2025.04.02 INTEL CORP
  • EP3885913B1 patent drawingFigure 1
  • EP3885913B1 patent drawingFigure 2A~2B
  • EP3885913B1 patent drawingFigure 3

AI summary

An apparatus comprising a first processor core to execute a first instance of an application; a second processor core to execute a second instance of the application concurrent with the execution of the first instance of the application; and processing circuitry to direct an interrupt to the first processor core based on an indication that an execution state of the first processor core is ahead of an execution state of the second processor core.