Interrupt Redirection for Multi-Threaded Error Domains
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Solution Overview
Problem
In multi-threaded computing systems, existing error handling mechanisms generate multiple corrected machine check interrupts for shared resources, leading to unnecessary OS overhead and inefficiencies, especially as processor architectures become more complex, and there is a need to redirect interrupts to only one thread execution context to maintain high reliability and availability.
Innovation Solution
The system employs a method to redirect corrected machine check interrupts to a single thread execution context within the error domain by maintaining lists of active thread execution contexts for each shared resource and dynamically updating the target context during system boot and runtime, ensuring that only one context receives interrupts, thus optimizing error handling and reducing overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple thread execution contexts receive corrected machine check interrupts for shared resources, then error detection coverage is improved, but system overhead and processing efficiency deteriorate
Solution Approach 1:
The patent segments the interrupt handling responsibility by dividing the error domain into specific thread execution contexts. Instead of having all threads receive interrupts, the system assigns specific error domains to specific threads, creating a segmented responsibility model that reduces redundant interrupt processing while maintaining comprehensive error coverage.
Solution Approach 2:
The patent introduces an intermediary mechanism (the interrupt redirection logic in firmware) that sits between the error detection hardware and the thread execution contexts. This intermediary redirects interrupts to the appropriate single thread context, preventing the overhead of multiple threads receiving and processing the same interrupt while ensuring reliable error detection.
2Reliability
If multiple thread execution contexts are assigned to handle errors for shared resources, then error handling robustness is improved, but system complexity increases
Solution Approach 1:
The patent extracts the interrupt redirection logic from the operating system into firmware (PAL/SAL layers). This extraction simplifies the overall system by removing the need for complex OS-level interrupt routing mechanisms, while maintaining robust error handling through the firmware's interrupt redirection capability.
Solution Approach 2:
The firmware layer provides self-service by automatically managing interrupt redirection to appropriate thread contexts without requiring complex OS intervention. The system self-regulates interrupt distribution, reducing the need for complex coordination mechanisms between multiple threads and the OS.
3Loss of information
If corrected machine check interrupts are delivered to all active thread execution contexts, then error visibility is improved, but processing time increases
Solution Approach 1:
The patent performs preliminary action by pre-assigning error domains to specific thread execution contexts before interrupts occur. This pre-assignment is maintained in data structures that the interrupt redirection logic uses to quickly determine the appropriate target thread, eliminating the need for time-consuming runtime decisions while ensuring complete error visibility to the responsible thread.
Data Source
AI summary
Disclosed is a communication mechanism among hardware, firmware and system software in order to redirect interrupts or other hardware events to only one thread execution context of an error domain for a multi-threaded processing system. Other embodiments are also described and claimed.