Interrupt Processing Register Allocation via Priority Lookup Table

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Solution Overview

Problem

Current interrupt processing methods are inefficient due to significant context switch times, which hinder high-speed operation in systems requiring rapid processing of interrupts, especially when handling interrupts with varying priorities.

Innovation Solution

The method involves using a look-up table to assign either a common or dedicated register based on interrupt priority, allowing context to be maintained in the common register for lower-priority interrupts, thereby minimizing context switching and enabling faster execution of higher-priority interrupts without switching contexts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If context switching is performed for every interrupt, then interrupt processing is completed, but processing time increases and system speed decreases

Engineering Contradiction:
Improveinterrupt processing completenessVSAvoidcontext switch time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the register file into multiple banks (e.g., Bank 0, Bank 1, Bank 2, Bank 3) that can be independently accessed. Each bank can store context for different interrupt levels, allowing the system to switch between interrupt contexts by selecting different banks rather than performing full context switches to memory, thereby reducing processing time while maintaining completeness.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent pre-allocates multiple register banks to store context information for different interrupt levels before interrupts occur. When an interrupt arrives, the system can immediately switch to the pre-prepared register bank corresponding to that interrupt level, eliminating the need to save and restore context from memory during interrupt handling, thus reducing time loss.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If dedicated registers are allocated for each interrupt, then interrupt processing speed increases, but device complexity increases

Engineering Contradiction:
Improveinterrupt processing speedVSAvoidregister management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent makes the register banks universal by allowing any register bank to serve any interrupt level through configurable mapping. The register banks can be dynamically assigned to different interrupt priorities based on system needs, providing multi-functionality without requiring dedicated registers for each interrupt, thus increasing processing speed while controlling complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent implements dynamic register bank allocation where the assignment of register banks to interrupt levels can be changed during system operation. This dynamic configuration allows the system to optimize interrupt processing speed for different scenarios without the rigidity of fixed dedicated registers, balancing speed improvement with manageable complexity through software-controlled allocation.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20240330038A1Method for processing interrupt and interrupt processing device
Publication Date: 2024.10.03 SAMSUNG ELECTRONICS CO LTD
  • US20240330038A1 patent drawing
  • US20240330038A1 patent drawing
  • US20240330038A1 patent drawing

AI summary

The present disclosure provides methods and apparatuses for interrupt processing. An interrupt processing method includes executing a first interrupt by using a common register, receiving a second interrupt and a second priority of the second interrupt during execution of the first interrupt, comparing a first priority of the first interrupt with the second priority of the second interrupt, generating a first register index corresponding to the second priority of the second interrupt by using a look-up table based on the second priority of the second interrupt being greater than the first priority, and, based on the first register index being a dedicated index, maintaining a context of the first interrupt stored in the common register, assigning a dedicated register for execution of the second interrupt, and executing an interrupt program corresponding to the second interrupt by using the assigned dedicated register. The interrupt program is saved in a memory.