Interrupt Scheduling Circuit for Cooperative Thread Utilization

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Cooperatively scheduled systems face challenges in efficiently managing processor utilization due to inefficient handling of interrupts, leading to increased activation overheads and reduced overall throughput.

Innovation Solution

A hardware scheduling circuit maintains an interrupt status indicator, such as a counter, to manage interrupt delivery and processing thread availability, using a doorbell mechanism to optimize when a user mode handler should yield the processor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If interrupts are delivered to processing threads in a cooperatively scheduled system, then system responsiveness is improved, but activation overhead increases and processor utilization decreases

Engineering Contradiction:

Improvesystem responsivenessVSAvoidactivation overhead

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The hardware scheduler pre-establishes interrupt affinity mappings between interrupts and processing threads before interrupts occur. This preliminary configuration allows interrupts to be directly routed to appropriate threads without requiring runtime context switches or activation overhead, thus maintaining system responsiveness while eliminating the time loss associated with dynamic scheduling decisions.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

A hardware doorbell mechanism acts as an intermediary between the interrupt source and processing threads. The doorbell register serves as a notification buffer that allows interrupters to signal pending interrupts without directly activating processing threads. This intermediary layer decouples the interrupt generation from thread activation, reducing overhead while maintaining responsiveness.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Speed

If processing threads are kept available to handle interrupts, then interrupt handling speed is improved, but processor utilization efficiency decreases

Engineering Contradiction:

Improveinterrupt handling speedVSAvoidprocessor utilization efficiency

Core Design Contradiction:

SpeedVSProductivity

Solution Approach 1:

The system assigns specific interrupts to specific processing threads based on affinity relationships established in the hardware scheduler. This local specialization allows processing threads to maintain cached state and context relevant to their assigned interrupts, improving interrupt handling speed for those specific interrupts while allowing other threads to be idle or perform unrelated work, thus maintaining overall processor utilization efficiency.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The hardware doorbell mechanism changes the notification parameter from direct thread activation to indirect signaling through register writes. Processing threads poll or are notified via doorbell registers rather than being directly activated by interrupt signals. This parameter change in the notification mechanism allows threads to control their own activation timing, improving interrupt handling speed when needed while avoiding unnecessary activations that would reduce processor utilization efficiency.

Inventive Principle:

Principle #35Parameter changes

3Measurement precision

If a hardware scheduling circuit maintains an interrupt status indicator, then interrupt management precision is improved, but system complexity increases

Engineering Contradiction:

Improveinterrupt management precisionVSAvoidsystem complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The hardware scheduling circuit maintains a simplified copy of interrupt status information in doorbell registers rather than implementing a full-fledged interrupt management subsystem. This copy contains only the essential status indicators needed for precise interrupt management (such as pending interrupt bits), providing measurement precision for interrupt states while avoiding the complexity of comprehensive interrupt control logic.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The patent replaces complex software-based interrupt management mechanisms with hardware-level indicators and doorbell registers. The interrupt status indicator is implemented as simple hardware bits rather than software data structures, and the doorbell mechanism uses direct hardware register writes instead of software notification protocols. This substitution provides precise interrupt management at the hardware level while significantly reducing overall system complexity by eliminating the need for complex software interrupt handling routines.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS12554531B2Improving processor utilization

Publication Date: 2026.02.17 MELLANOX TECHNOLOGIES LTD(IL)

AI summary

Techniques described herein include managing scheduling of interrupts by receiving a data packet comprising an indication of an interrupt to be delivered, determining an availability status of a processing thread, and managing an interrupt status indicator in response to determining the availability status. A value of the interrupt status indicator corresponds to a quantity of pending interrupts. An event handling circuit processes the interrupt or one or more pending interrupts using the processing thread.