Interrupt Controller Segmentation Arbitration
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Solution Overview
Problem
Traditional interrupt controllers face challenges in efficiently processing a large number of interrupts from multiple sources, leading to increased resource requirements and complex timing phasing, which affects timing performance and chip size.
Innovation Solution
The proposed interrupt controller employs a sampling unit to sample interrupts and a priority arbitration unit to split interrupts into segments, determine the highest priority interrupt within each segment, and iteratively perform arbitration to identify the to-be-responded-to interrupt, thereby reducing the arbitration logic resources needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional interrupt control is used with a large quantity of interrupt sources, then the interrupt controller can process more interrupts, but the resources for priority arbitration expand rapidly and the design becomes highly complicated
Solution Approach 1:
The patent divides the interrupt arbitration process into multiple stages. In the first stage, interrupt signals are divided into multiple groups and arbitrated separately using simple arbitration logic. In the second stage, the winners from each group are further arbitrated to determine the final highest priority interrupt. This segmentation allows the system to handle a large number of interrupt sources (more than 512) using a small quantity of arbitration resources, as each stage uses only a subset of the total interrupts for arbitration.
2Adaptability or versatility
If traditional interrupt control is used with a large quantity of interrupt sources, then the interrupt controller can process more interrupts, but timing phasing becomes complicated and affects timing performance
Solution Approach 1:
The patent segments the interrupt arbitration into multiple independent stages, where each stage processes a subset of interrupts simultaneously. This allows timing phasing to be simplified at each stage rather than managing phasing for all interrupts at once. The sampling unit samples interrupts at specific timing phases, and the arbitration stages proceed in a phased manner, reducing the overall timing complexity while maintaining the ability to handle many interrupt sources.
3Adaptability or versatility
If traditional interrupt control is used with a large quantity of interrupt sources, then the interrupt controller can process more interrupts, but the chip size increases
Solution Approach 1:
The patent implements multi-stage arbitration where each stage uses a small portion of the total interrupt signals. The first stage arbitrates multiple groups of interrupts simultaneously using a small number of comparators and selectors. Only the winners from each group proceed to the second stage. This segmentation dramatically reduces the total number of arbitration resources needed compared to a single-stage approach that would require resources proportional to the square of the number of interrupt sources, thereby reducing chip area.
Solution Approach 2:
The patent transitions from a single-stage arbitration approach to a multi-stage approach, adding the dimension of time (arbitration stages) to reduce the resource requirements in each individual stage. By distributing the arbitration process across multiple time-phased stages, the system achieves the same functionality with significantly reduced resources, directly reducing chip size.
Data Source
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AI summary
The present invention discloses an interrupt controller, including: a sampling unit adapted to receive interrupts from various interrupt sources coupled to the interrupt controller and perform sampling on the received various interrupts; and a priority arbitration unit adapted to classify the received various interrupts into a plurality of interrupt segments, where each interrupt segment includes one or more sampled interrupts, and determine, segment by segment, an interrupt with the highest priority in a selected segment, until an interrupt with the highest priority among all interrupts is identified through arbitration and used as an to-be-responded-to interrupt. The present invention further discloses a processor including the interrupt controller, and a system-on-chip.