Interrupt Shadow Copy Race Condition Resolution

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Solution Overview

Problem

Message-based delivery of interrupts over a data interconnect fabric in computing systems can result in race conditions due to communication latency, leading to incorrect handling of interrupts with changing task priorities and enable values.

Innovation Solution

Implementing a shadow copy comparison mechanism for frequently changing interrupt control values and a danger flag mechanism for infrequently changing values to ensure accurate interrupt handling by maintaining a shadow copy of interrupt control values near the processing unit and setting a danger flag when updates occur, allowing for low-latency comparison and detection of potential race conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If message-based delivery of interrupts over data interconnect fabric is used, then system scalability and flexibility are improved, but race conditions occur due to communication latency

Engineering Contradiction:

Improvesystem scalabilityVSAvoidinterrupt handling accuracy

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies preliminary action by maintaining shadow copies of interrupt control values (task priority, interrupt enable) in the L2 cache before they are updated in the interrupt controller. This allows the processing unit to compare the shadow copy with the value received in the interrupt message, detecting race conditions before they cause incorrect interrupt handling. The shadow copy is prepared in advance and kept synchronized with the interrupt controller's values.

Inventive Principle:

Principle #10Preliminary action

2Speed

If interrupt control values are updated frequently, then system responsiveness is improved, but race conditions between update messages and interrupt messages increase

Engineering Contradiction:

Improvesystem responsivenessVSAvoidinterrupt priority accuracy

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent uses copying by creating and maintaining shadow copies of interrupt control values in the L2 cache. When the processing unit receives an interrupt message, it compares the task priority value in the message with the shadow copy stored in the L2 cache. If they differ, a race condition is detected and the interrupt is handled accordingly. This copying mechanism allows frequent updates without losing accuracy.

Inventive Principle:

Principle #26Copying

3Measurement precision

If shadow copy comparison mechanism is implemented, then race condition detection accuracy is improved, but device complexity increases

Engineering Contradiction:

Improverace condition detection accuracyVSAvoidinterrupt handling mechanism complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies universality by using the L2 cache, which is an existing component in the processing unit, to store shadow copies of interrupt control values. The L2 cache serves its normal function of storing frequently accessed data while also functioning as a storage location for shadow copies. This multi-functionality avoids adding dedicated hardware for shadow copy storage, thereby reducing the increase in device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11341069B2Distributed interrupt priority and resolution of race conditions

Publication Date: 2022.05.24 ADVANCED MICRO DEVICES INC

AI summary

A method of operating a processing unit includes storing a first copy of a first interrupt control value in a cache device of the processing unit, receiving from an interrupt controller a first interrupt message transmitted via an interconnect fabric, where the first interrupt message includes a second copy of the first interrupt control value, and if the first copy matches the second copy, servicing an interrupt specified in the first interrupt message.