Interrupt Source Identification in Multi-CPU Shared Memory Systems
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Solution Overview
Problem
In large-scale computer systems with multiple CPUs, cross calls often take longer to complete, leading to time-outs and system instability, and there is a need for efficient communication and prioritization between CPUs to prevent processing delays and competition.
Innovation Solution
An information processing apparatus and method that includes a data transmission processing unit, an interrupt generating unit, and an interrupt processing unit, which store and transmit data with identification information specifying the storage area, allowing CPUs to efficiently identify interrupt sources and prioritize data access, thereby reducing processing delays and competition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of CPUs is increased to form a large-scale computer system, then the computing power and processing capability are improved, but the cross call time increases and system reliability deteriorates due to time-outs
Solution Approach 1:
The patent segments the shared memory into multiple storage areas, each associated with specific CPUs. This segmentation allows CPUs to quickly identify which storage area to access based on the interrupt source, reducing cross call time and preventing time-outs in large-scale systems with many CPUs.
Solution Approach 2:
The patent pre-establishes the correspondence between storage areas and CPUs before cross call operations occur. By preliminarily organizing memory resources and setting up identification mechanisms, the system enables rapid data transfer without extensive searching during actual cross calls, thereby improving reliability.
2Productivity
If data is transmitted to the same CPU from multiple BBs, then data communication capability is improved, but cross access competition occurs causing processing delays
Solution Approach 1:
The patent divides the shared memory into distinct storage areas for different BBs, even when transmitting to the same CPU. This segmentation eliminates cross access competition by providing dedicated storage regions, allowing multiple BBs to write data simultaneously without conflict, thus maintaining high communication capability without processing delays.
3Device complexity
If the interrupt destination is determined without storage area identification, then device complexity is reduced, but the transmission destination CPU cannot efficiently judge the interrupt source
Solution Approach 1:
The patent extracts storage area identification information from the interrupt signal and transmits it to the destination CPU. This extracted identification enables the destination CPU to efficiently determine which storage area contains the data without complex global searching, improving interrupt source identification speed while keeping the overall system relatively simple.
Data Source
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AI summary
A first computing device includes a data transmission processing unit (12) transmitting data to be transferred to another computing device to a first storage area among the plurality of storage areas (25), and an interrupt generating unit (14) generating an interrupt corresponding to transmission of data by the data transmission processing unit (12) with respect to a transmission destination of the data together with identification information specifying the storage area (25), and a second computing device includes an interrupt processing unit (23) specifying from which computing device the interrupt is requested based on the identification information received together with the interrupt when receiving the interrupt, and a data receiving unit (22) reading out data from the first storage area (25) corresponding to the computing device specified by the interrupt processing unit (23) among the plurality of storage areas (25) to efficiently communicate among computing devices in an information processing apparatus including a plurality of computing devices.