Interrupt Steering Across Heterogeneous Cores for Power-Aware Arbitration
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Solution Overview
Problem
In heterogeneous processor architectures, assigning interrupts based on availability and priority in homogeneous systems can adversely affect power and performance, leading to inefficient core selection.
Innovation Solution
Implement arbitrated interrupt steering that selects processors based on power efficiency, prioritizing high-efficiency cores when possible, and high-performance cores when needed, using a control circuit to manage interrupt assignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If interrupts are assigned to processors based on availability and priority in heterogeneous processor architectures, then interrupt handling follows simple homogeneous processor rules, but power efficiency and performance are adversely affected
Solution Approach 1:
The patent changes the arbitration parameters from simple priority-based selection to a comprehensive evaluation that includes processor type (high-performance vs. high-efficiency), power state, and workload characteristics. This allows the system to select appropriate processors based on both performance requirements and power efficiency, resolving the contradiction between simple assignment rules and power efficiency.
Solution Approach 2:
The interrupt arbitration mechanism dynamically adapts its selection criteria based on current system conditions, including which processors are in low-power states, current workload profiles, and performance requirements. This dynamic behavior allows the system to optimize power efficiency without sacrificing necessary performance, as the arbitration strategy changes based on real-time conditions.
2Productivity
If high-performance processors are used for all interrupts to ensure performance, then performance requirements are met, but power consumption increases
Solution Approach 1:
The patent applies different processor types to different interrupts based on their specific requirements. High-performance processors are used only when necessary (for performance-critical interrupts), while high-efficiency processors handle routine interrupts. This localized application of processor capabilities optimizes the balance between performance and power consumption.
Solution Approach 2:
The system changes the operational parameters of processors by putting them into low-power states when not needed and selectively activating high-performance processors only when performance is required. This parameter change approach allows the system to minimize power consumption while maintaining performance when necessary.
3Use of energy by moving object
If high-efficiency processors are prioritized for power savings, then power efficiency improves, but performance may be compromised when high-performance is required
Solution Approach 1:
The arbitration mechanism dynamically switches between prioritizing power efficiency and prioritizing performance based on interrupt characteristics and system conditions. When performance is required, the system can override the default power-efficient selection and assign interrupts to high-performance processors, ensuring that power savings do not compromise necessary performance.
Solution Approach 2:
The system incorporates feedback mechanisms that monitor performance requirements and power states, allowing it to adjust interrupt assignment decisions in real-time. This feedback ensures that when performance is required, the system can select appropriate high-performance processors, while maintaining power efficiency for non-critical interrupts.
Data Source
AI summary
The disclosed device includes a heterogeneous processor architecture having heterogeneous processors, and a control circuit that can assign, in response to an interrupt, the interrupt to one of the heterogenous processors that is selected based on power efficiency. Various other methods, systems, and computer-readable media are also disclosed.