Interrupt Table Mediator for Virtualized Processor Routing
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Solution Overview
Problem
In multiprocessor computer systems, efficiently routing interrupts from bus-connected modules to the appropriate processor is challenging, especially when communicating with a guest operating system on a virtual machine, as the mapping between virtual and logical processor IDs is dynamic and not known to the guest operating system, leading to inefficiencies in interrupt handling.
Innovation Solution
Implementing a method where the bus attachment device directly addresses a target processor using a logical processor ID, with an interrupt table mapping interrupt target IDs to logical processor IDs, and utilizing message signaled interrupts (MSI-X) to forward interrupts directly to the appropriate processor, minimizing cache traffic and avoiding broadcast interruptions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If broadcasting is used to forward interrupt signals between multiple processors, then the interrupt signal can reach a suitable processor, but the interrupt handling efficiency deteriorates due to successive forwarding and low probability of direct match
Solution Approach 1:
An interrupt table is introduced as an intermediary data structure that maps interrupt target IDs to logical processor IDs. The bus attachment device queries this table to translate interrupt target IDs into direct processor addresses, eliminating the need for successive broadcast forwarding while ensuring reliable interrupt delivery to the appropriate processor.
Solution Approach 2:
The interrupt table is pre-populated with mappings between interrupt target IDs and logical processor IDs before interrupt handling occurs. This preliminary setup allows the bus attachment device to directly determine the target processor without iterative searching or broadcasting, thereby improving interrupt handling efficiency while maintaining reliability.
2Adaptability or versatility
If the hypervisor dynamically changes the mapping between virtual and logical processor IDs, then system adaptability improves, but interrupt routing complexity increases due to dynamic remapping requirements
Solution Approach 1:
The interrupt table serves as a mediator between the dynamic hypervisor processor mappings and the interrupt routing mechanism. When the hypervisor changes virtual-to-logical processor mappings, only the interrupt table needs to be updated, not the entire interrupt routing infrastructure. This isolates the complexity to a single data structure while maintaining simple routing logic.
Solution Approach 2:
The interrupt table is designed to be dynamically updateable, allowing the hypervisor to modify mappings between interrupt target IDs and logical processor IDs at runtime. This dynamic capability enables flexible processor assignment and load balancing while keeping the interrupt routing mechanism itself simple and unchanged.
Data Source
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AI summary
The invention relates to a method for providing an interrupt signal to a guest operating system executed using one or more processors of a plurality of processors. One or more bus connected modules are operationally connected with the plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from one of the bus connected modules with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device translates the received interrupt target ID to a logical processor ID of the target processor using an interrupt table entry stored in a memory operationally connected with the bus attachment device and forwards the interrupt signal to the target processor for handling. The logical processor ID of the target processor is used to address the target processor directly.