Interrupt Transfer Logic for Multiprocessor Systems
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Solution Overview
Problem
In multi-processor systems, low-priority interrupts like timeouts often face delays due to being processed by a single overloaded processor, leading to inefficiencies and potential system malfunctions as they wait for the processor to become available, while higher priority interrupts are handled first.
Innovation Solution
The solution involves migrating low-priority interrupts from a busy processor to another available processor, allowing for quicker processing by distributing the workload across multiple processors, thereby reducing wait times and improving system efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-priority interrupts are processed by a single processor following priority queues, then higher priority interrupts are handled first, but low-priority interrupts experience long delays and potential system malfunctions
Solution Approach 1:
The patent divides the interrupt processing workload across multiple processors by segmenting the single-processor queue into multiple processor-specific queues. Each processor maintains its own priority queue, and a timeout interrupt can be transferred from one processor's queue to another's queue, effectively segmenting the processing load and reducing congestion at any single processor.
Solution Approach 2:
The patent introduces an intermediary mechanism (the interrupt transfer logic and status flags) that enables timeout interrupts to move between processor queues. This intermediary system allows low-priority interrupts to be redirected from overloaded processors to available processors, mediating the conflict between maintaining priority processing and reducing wait times.
2Productivity
If multiple processors are available to handle interrupts, then system efficiency can be improved, but the complexity of interrupt management increases
Solution Approach 1:
The patent implements self-service mechanisms where each processor autonomously manages its own interrupt queue and can independently transfer timeout interrupts to other processors based on queue status flags. This distributes the management complexity across multiple processors rather than requiring a centralized controller, improving productivity while managing complexity through decentralization.
Solution Approach 2:
The patent changes the state parameters of interrupt queues by introducing status flags that indicate whether a queue is empty or contains pending interrupts. These parameter changes enable automatic decision-making for interrupt transfer without complex management logic, allowing multiple processors to work together efficiently while keeping the management system relatively simple.
Data Source
AI summary
Apparatus and methods are provided for transferring interrupts. One embodiment of a computing device includes a first processor, a memory in communication with the first processor, and computer executable instructions stored in memory and executable on the first processor. The computer executable instructions are provided to select an interrupt, that has been waiting to be processed, for transfer from the first processor, check a number of other processors to select a second processor that has a short wait time for processing the interrupt, and transfer the interrupt from the first processor to the second processor.