Interrupt Vector Table Segmentation for Secure Sleep State Wakeup
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Solution Overview
Problem
Existing technologies for storing interrupt processing addresses in write-once logic circuits lack flexibility, as they cannot be corrected, and are vulnerable to address falsification, making it difficult to securely change interrupt addresses while executing certain interrupt processing.
Innovation Solution
An information processing device with a processor, controller, and memory that stores interrupt vector addresses, allowing the controller to detect the processor's sleep state and input the correct vector address for secure interrupt processing, ensuring secure execution even if interrupt vector addresses are falsified.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interrupt vector addresses are stored in a write-once logic circuit, then the addresses cannot be falsified and security is improved, but the addresses cannot be corrected and flexibility is worsened
Solution Approach 1:
The interrupt vector table is divided into two separate regions: a first region with read-only attributes storing secure interrupt vectors that cannot be modified, and a second region with read-write attributes storing interrupt vectors that can be modified. This segmentation allows simultaneous achievement of security for critical interrupts and flexibility for others.
Solution Approach 2:
Different regions of the interrupt vector table are assigned different security attributes locally. The first region has read-only quality for high-security requirements, while the second region has read-write quality for flexibility requirements. This local differentiation resolves the contradiction between overall security and flexibility.
2Reliability
If all interrupt processing addresses are stored in a write-once circuit, then security against falsification is improved, but the ability to change addresses for different interrupt processing is worsened
Solution Approach 1:
The interrupt vector table is segmented into multiple regions with different accessibility attributes. The first region uses read-only attributes to prevent falsification of critical interrupt addresses, while the second region uses read-write attributes to allow modification of other interrupt addresses, thus resolving the contradiction between security and adaptability.
Solution Approach 2:
The system transitions from a static write-once storage model to a dynamic model where different regions have different mutability characteristics. Critical regions remain static for security, while non-critical regions can be dynamically modified, allowing the system to adapt to changing requirements without compromising security.
3Adaptability or versatility
If interrupt vector addresses are made changeable, then flexibility is improved, but the risk of address falsification by malicious programs is worsened
Solution Approach 1:
By segmenting the interrupt vector table into read-only and read-write regions, the system allows flexibility in the second region while protecting the first region from malicious modification. This segmentation ensures that even if the second region is compromised, critical interrupts in the first region remain secure.
Solution Approach 2:
The read-only attribute is applied in advance to critical interrupt vector regions to prevent malicious programs from falsifying these addresses. This preliminary protective measure blocks potential attacks before they can occur, while still allowing non-critical regions to remain flexible.
Data Source
AI summary
According to one embodiment, an information processing device includes a processor, a controller, and a memory. The memory stores a vector address related to an interrupt request executed on condition that the processor is in a sleep state. The controller receives the interrupt request and detects that the processor transitions to the sleep state, detects fetch of the vector address of the interrupt request after the sleep state of the processor is detected, and inputs the vector address that is related to the interrupt request and stored in the memory into the processor in a case where the fetch of the vector address of the interrupt request is detected.