Interrupted Small Block Shape for Semiconductor Cell Boundary Definition
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Solution Overview
Problem
Conventional photolithographic processes struggle to scale semiconductor devices beyond 6 tracks due to lithographic overlay tolerances, leading to shorting of wiring lines and inefficient use of chip area, as they cannot effectively separate cut metal lines to prevent device shorting.
Innovation Solution
A method involving multiple lithography steps and etching processes to form cut metal lines that define cell boundaries, allowing for reduced track count and smaller technology nodes by using a combination of masks and selective etching to create interruptions in wiring lines, enabling vertical metal wiring routing and reducing cell height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithographic processes are used to scale devices, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to lithographic overlay tolerances causing shorting of wiring lines
Solution Approach 1:
The patent divides the cell boundary formation into two separate lithography steps: first forming the cell boundary pattern, then forming the metal line pattern. This segmentation allows each step to be optimized independently, achieving the required separation precision (greater than minimum pitch) without compounding overlay errors from a single complex lithography step.
Solution Approach 2:
The cell boundary pattern is formed in advance as a preliminary structure before metal line deposition. This preliminary action establishes the separation geometry that prevents shorting, and the metal lines are subsequently conformal to this pre-established boundary, ensuring proper spacing is maintained throughout the process.
2Area of stationary object
If track count is reduced to improve area scaling, then area efficiency improves, but manufacturing precision deteriorates due to difficulty in maintaining separation beyond 6 tracks
Solution Approach 1:
By segmenting the boundary formation into two lithography steps, the patent enables reduced track count designs while maintaining the required separation precision. Each lithography step can be independently optimized to achieve the necessary spacing, allowing track reduction beyond the conventional 6-track limit without compromising manufacturing precision.
Solution Approach 2:
The patent transitions from a single-planar lithography approach to a multi-layer approach where the cell boundary and metal lines are formed in separate lithography layers. This dimensional separation allows for tighter spacing and reduced track count while maintaining the required separation precision through the use of multiple patterning layers.
3Area of moving object
If feature size is reduced to improve density, then area scaling improves, but manufacturing precision deteriorates as conventional lithography cannot keep up with current scaling
Solution Approach 1:
The patent segments the patterning process into two independent lithography steps, each operating at relaxed pitch requirements. This allows the first step to form the cell boundary at a larger effective pitch, and the second step to form metal lines conformal to that boundary, both within conventional lithographic capabilities, thereby achieving reduced feature sizes without compromising manufacturing precision.
Solution Approach 2:
The cell boundary is formed as a preliminary pattern at a larger dimension that is within the capabilities of conventional lithography. This preliminary structure then serves as a template for the subsequent metal line formation, allowing feature size reduction to be achieved through the conformal relationship rather than direct lithographic patterning at the final small dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the fabrication of smaller semiconductor structures with reduced cell height and increased density, overcoming the limitations of conventional scaling by allowing for reliable separation of metal lines and efficient use of chip area, while maintaining reliable metal line integrity.
Implementation Method 1
defining a pattern in a first mask over a dielectric material; defining a pattern in a second mask, superimposed over the first mask; patterning the block material with a lithography step
Implementation Method 2
anisotropically etching the material to form an overhang on the block material and covering a portion of the notched feature; etching exposed portions of the block material with the overhang protecting the dielectric material and block material underneath the overhang
Implementation Method 3
filling the trenches with metal material to form at least cut wiring structures defining a cell boundary; filling the layout with metal material to form at least cut wiring structures
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to interrupted small block shape structures (e.g., cut metal lines forming cell boundaries) and methods of manufacture. The structure includes: a plurality of wiring lines with cuts that form a cell boundary; and at least one wiring line extending beyond the cell boundary and which is continuous from cell to cell.