Interrupted Through-Silicon-Vias for Stacked IC Identification
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Solution Overview
Problem
Existing stacked integrated circuit arrangements using Through Silicon Via (TSV) technology face challenges in uniquely identifying individual chips within a stack, leading to inefficiencies and increased power dissipation due to unconnected inputs and noise issues, particularly in memory devices connected via continuous vertical TSVs.
Innovation Solution
The implementation of interrupted TSVs that terminate within the active circuit and interconnect region, allowing for serial connections without die rotation, enabling unique chip identification through staggered TSV arrangements and binary encoding, which reduces the need for additional logic and enhances flexibility in TSV placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If continuous vertical TSVs are used for stacking memory chips, then high connectivity and simple stacking process are achieved, but unique chip identification becomes difficult and power dissipation increases due to unconnected inputs and noise
Solution Approach 1:
The patent divides the continuous TSV connection into segmented connections by introducing interruption points within the active circuit and interconnect region. This segmentation allows the TSV to connect to different circuit nodes at different levels, enabling unique chip identification while maintaining manufacturing simplicity. The interrupted TSV structure breaks the continuous vertical path into controlled segments that can be selectively connected to identification logic.
Solution Approach 2:
The patent applies local quality by creating different connection characteristics at different locations within the TSV structure. The TSV maintains continuous connection in regions requiring high connectivity while introducing interruptions at specific locations where identification logic is needed. This localized modification allows the same TSV structure to serve dual purposes: general interconnection and unique chip identification.
2Reliability
If interrupted TSVs are implemented to enable unique chip identification, then chip identification capability and noise reduction are improved, but manufacturing complexity increases
Solution Approach 1:
The patent introduces asymmetry in the TSV structure by creating non-uniform connection patterns at different chip levels. The interrupted TSVs are positioned and configured asymmetrically relative to the chip stack, allowing each chip to have a unique identification signature. This asymmetric arrangement enables differentiation between chips while the underlying TSV fabrication process remains relatively simple and scalable.
3Productivity
If TSV density is increased to achieve wider busses, then connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent extracts the identification function from the main data bus by using separate interrupted TSV connections dedicated to chip identification. This separation allows the main TSV array to focus on high-density data transmission while a smaller subset of interrupted TSVs handles identification. By taking out the identification requirement, the system can achieve high bus width without proportionally increasing the precision demands on all TSVs.
Data Source
AI summary
In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.