Interruptible Run-Time BIST for Processor Idle Slots
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Solution Overview
Problem
Existing methods for testing mission-critical electronic devices during extended operational periods are inadequate, as they often fail to detect failures in a timely manner and can disrupt the device's performance, especially in safety-related processes.
Innovation Solution
The implementation of an interruptible non-destructive run-time built-in self-test (IRT-BIST) system, which interleaves test operations during normal functional operations in small, idle time slots, allowing for continuous monitoring without disrupting the device's functionality, using a BIST controller that scans test patterns and evaluates results without affecting the processor's performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power-up testing is used to detect faults, then device complexity is reduced, but fault detection latency increases
Solution Approach 1:
The system performs preliminary testing actions during idle timeslots before actual failures occur. The BIST controller continuously monitors and executes test patterns during available idle periods, so that when a failure occurs, it has already been detected. This preliminary continuous monitoring during idle periods eliminates the delay inherent in waiting for power-up cycles.
Solution Approach 2:
The system implements periodic testing by executing test patterns at regular intervals during idle timeslots. Instead of single power-up testing, the BIST controller performs repeated test cycles throughout operation, ensuring failures are detected promptly while maintaining systematic periodic monitoring that balances reliability with operational continuity.
2Reliability
If continuous testing is performed during extended operational periods, then fault detection latency is reduced, but device complexity increases
Solution Approach 1:
The testing function is extracted as a separate BIST controller component that operates independently from the main processor. This modular extraction allows continuous monitoring capability to be added without significantly increasing the complexity of the core processing system. The BIST controller uses existing scan chains and test infrastructure, reusing components rather than adding entirely new complex systems.
Solution Approach 2:
The BIST controller serves multiple functions: it monitors processor health, executes test patterns, captures results, and manages idle timeslot coordination. By making the testing system multi-functional and integrating it with existing processor infrastructure (scan chains, test ports), the solution achieves continuous monitoring without proportional increases in overall device complexity.
3Productivity
If test operations are interleaved during normal functional operations, then productivity is maintained, but measurement precision may be affected
Solution Approach 1:
The testing process is segmented into discrete test patterns executed during separate idle timeslots. Each test pattern is self-contained and executes atomically during its designated idle period, isolating measurement activities from normal operational interference. This segmentation ensures test results are not corrupted by concurrent operations while maintaining continuous system productivity.
Solution Approach 2:
The BIST controller acts as an intermediary that mediates between normal operational operations and testing operations. It coordinates test execution during idle timeslots, manages the transition between test and operational modes, and ensures proper isolation of test measurements from operational activities. This intermediary control maintains both productivity and measurement precision by properly managing the interaction between testing and normal operations.
Data Source
AI summary
A built-in self-test (BIST) diagnostic system tests the execution of a processor. The processor is arranged to execute a normal application for controlling a process that is external to the processor. The normal execution is executed in normal execution timeslots that have idle timeslots that are interspersed in time between the normal execution timeslots. A BIST controller is arranged to detect the presence of an idle timeslot in the execution of the processor and to use a scan chain to scan-in a first test pattern for a test application for testing the processor. The first test pattern is executed by the processor during the detected idle timeslot and a first result pattern generated by the execution of the first test pattern is scanned-out. The scanned-out first test pattern is evaluated to determine the presence of an error. The first test pattern application is conditionally interruptible.