Interruptible Internal Transfer in DRAM Memory Controllers
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Solution Overview
Problem
Existing memory systems face inefficiencies in power consumption and channel bandwidth during block data copy operations, as they lack the ability to interrupt and manage internal transfer operations effectively.
Innovation Solution
The implementation of an integrated circuit memory device with command interface circuitry that receives internal transfer commands, allowing for pause and abort of in-process operations, and utilizing a memory command protocol that supports interruptible internal transfer operations, thereby reducing interface power and increasing channel bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If block data copy operations are performed using existing memory systems, then data manipulation capability is provided, but interface power consumption increases and channel bandwidth is reduced
Solution Approach 1:
The memory device is divided into multiple banks that can operate independently. Block data copy operations are segmented to occur within banks or between banks without requiring continuous external interface involvement, thereby reducing interface power consumption while maintaining data transfer capability through internal transfer mechanisms.
Solution Approach 2:
An internal transfer mechanism acts as an intermediary between memory banks, enabling data copying operations to occur internally without continuously engaging the external interface. This intermediary internal transfer path reduces interface power consumption and prevents bandwidth contention by handling data movement within the memory device itself.
2Adaptability or versatility
If interruptible internal transfer operations are implemented, then high-priority operations can be paused during internal transfers, but device complexity increases
Solution Approach 1:
The memory device implements dynamic operation prioritization where the priority of transfer operations can change during execution. Interruptible internal transfer operations allow high-priority operations to pause ongoing transfers, and the system dynamically resumes the original operation after the high-priority operation completes, providing adaptability without requiring complete redesign of the control architecture.
Solution Approach 2:
The interruptible transfer mechanism uses periodic checking and resumption points within the data transfer process. The system periodically checks for interrupt conditions and can pause at predefined points in the transfer operation, then resume afterward. This periodic action structure provides operation prioritization capability while keeping control logic complexity manageable through standardized pause and resume protocols.
Data Source
AI summary
Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory device is disclosed. The memory device includes an array of storage cells and command interface circuitry to receive an internal transfer command. In response to the internal transfer command, transfer logic reads data from a first portion of the array of storage cells, transfers the data as on-chip transfer data, and writes the on-chip transfer data to a second portion of the array of storage cells. In response to the command interface circuitry receiving an interrupt command, the transfer logic pauses the internal transfer operation, and carries out an unrelated memory access operation involving at least the first portion of the array of storage cells or the second portion of the array of storage cells.