Single-Instruction HMAC Processing With Interruptible Hash Execution

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Solution Overview

Problem

Existing cryptographic hash-based message authentication code processing is inefficient due to the need for multiple passes and separate determinations of processing interruptions, leading to high latency and software processing overhead.

Innovation Solution

A single instruction, such as the compute message authentication code instruction, is used to perform hash-based message authentication code processing, allowing for interruption and resumption without compromising security, utilizing hardware accelerators to maintain state information and reduce latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple passes of hash computation are performed with separate key derivations, then cryptographic security is maintained, but processing time and latency increase

Engineering Contradiction:

Improvecryptographic securityVSAvoidprocessing latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent combines multiple separate hash computation passes and key derivation operations into a single integrated instruction execution. The hardware accelerator performs inner-key padding, outer-key padding, and both hash passes in one continuous operation, eliminating the time loss from separate software invocations while maintaining cryptographic security through the same multi-pass HMAC structure.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent replaces the software-based multi-pass processing mechanism with a hardware accelerator that executes a single specialized instruction. This substitution eliminates software overhead and context switching between passes, reducing processing latency while the hardware logic internally maintains the secure multi-pass cryptographic structure.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Adaptability or versatility

If separate software processing is used for each hash pass, then flexibility and control are maintained, but software processing overhead increases

Engineering Contradiction:

Improveprocessing flexibilityVSAvoidsoftware processing overhead

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent replaces complex software processing sequences with a single hardware accelerator instruction. The hardware device is configured to perform inner-key padding, outer-key padding, and both hash computation passes atomically in one operation, eliminating multiple software function calls, parameter passing, and control flow management while maintaining cryptographic correctness.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The hardware accelerator implements a universal instruction that handles the entire HMAC computation process including both key derivations and both hash passes. This single multi-functional instruction replaces multiple specialized software functions, reducing overhead while maintaining the flexibility to handle different message inputs and cryptographic parameters.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If traditional multi-pass processing is used, then correct authentication code generation is ensured, but processing throughput decreases

Engineering Contradiction:

Improveauthentication code correctnessVSAvoidprocessing throughput

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent merges the sequential multi-pass processing into a single parallelizable hardware operation. The hardware accelerator executes inner-key padding, outer-key padding, first hash pass, and second hash pass in one continuous throughput-optimized operation, maintaining authentication code correctness through verified cryptographic logic while increasing processing throughput by eliminating inter-pass overhead.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent substitutes software-based sequential processing with hardware-based parallel execution. The hardware accelerator uses dedicated logic circuits to perform all HMAC operations simultaneously in one clock cycle or few cycles, ensuring cryptographic correctness through hardwired logic while achieving high throughput by eliminating software interpretation overhead and enabling pipeline parallelism.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS20260005850A1Instruction to accelerate hash-based message authentication code processing

Publication Date: 2026.01.01 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

An instruction is executed to generate an authentication code. Executing the instruction includes performing a plurality of operations of the instruction to generate the authentication code. The plurality of operations includes performing a sequence of hash operations on a message to generate an intermediate message digest, and performing an outer-key padding and hashing operation using the cryptographic key to generate another output chaining value to be used in generating a final output message digest based on a final input message digest produced using the intermediate message digest. The final output message digest being a resulting authentication code. The performing the sequence of hash operations and the outer-key padding and hashing operation are performed as part of a single invocation of the instruction.