Interruptible Memory Command Logic for Read Latency Reduction
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Solution Overview
Problem
High-speed memory systems face significant latency issues due to the inability to interrupt and prioritize command sequences, particularly during write operations, which hinders mission-critical read operations and increases system delay.
Innovation Solution
A memory device with command logic that allows for the interruption of a first command sequence, such as a page write, and enables immediate processing of a higher priority second command sequence, like a read, without completing the first sequence, using control signals on a chip select line to manage and resume the interrupted operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory device completes the first command sequence (page write) before processing the second command sequence (read), then the write operation is ensured to complete successfully, but the read latency increases significantly
Solution Approach 1:
The patent implements dynamic command sequence handling where the memory device can transition between different operational states (receiving commands, executing commands, suspended state) based on incoming interrupt signals. The command logic dynamically adjusts the execution flow by detecting interrupt conditions mid-sequence and switching to alternative execution paths that prioritize higher-priority commands while maintaining the ability to resume lower-priority operations later.
Solution Approach 2:
The patent segments the command sequence processing into distinct phases: command reception phase, execution phase, and resumption phase. By segmenting the write operation into an interruptible portion (command reception and initial execution) and a resumable portion (completion after interrupt), the system can interleave read operations without completely abandoning the write operation, thus reducing read latency while preserving write reliability.
2Stability of the object's composition
If the memory device waits for the first command sequence to complete before accepting the second command sequence, then command execution order is maintained, but system productivity decreases
Solution Approach 1:
The patent implements preliminary interrupt detection and command buffering mechanisms. When an interrupt signal is detected during command sequence execution, the system preliminarily suspends the current sequence, buffers its state, and prepares to execute the higher-priority command immediately. This preliminary action allows the system to maintain command integrity while improving throughput by not forcing sequential completion.
Solution Approach 2:
The patent changes the operational parameters of command sequence handling by introducing interruptible states and priority-based scheduling. The system transitions from a fixed sequential execution model to a flexible parameter-driven model where command priority, interrupt status, and execution state become dynamic parameters that determine the actual execution order, thereby increasing system productivity without compromising stability.
3Stability of the object's composition
If the memory device requires the chip select signal to remain stable throughout the first command sequence, then signal integrity is maintained, but the ability to issue interrupt signals is restricted
Solution Approach 1:
The patent resolves the signal stability conflict by operating in multiple temporal dimensions. The chip select signal maintains its stable logical state (selected or deselected) while the system processes commands across different time phases within that state. Interrupt signals are accommodated as temporal events that occur within the stable chip select window, allowing the signal integrity to be maintained while enabling interrupt functionality through temporal dimensionality.
Solution Approach 2:
The patent introduces the command logic as an intermediary layer between the chip select signal and the command execution engine. This intermediary monitors both the chip select signal stability and incoming interrupt signals, mediating between the two requirements by detecting interrupts during stable periods and scheduling their processing appropriately, thus maintaining signal integrity while enabling interrupt capability.
Data Source
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Figure 2
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AI summary
A memory device includes command logic allowing for a command protocol allowing interruption of a first command sequence, such as a page write sequence, and then to proceed directly to receive and decode a second command sequence, such as a read sequence, without latency associated, completing the first command sequence. Also, the command logic is configured to be responsive to a third command sequence after the second command sequence and its associated embedded operation have been completed, which completes the interrupted first command sequence and enables execution of an embedded operation identified by the first command sequence. A memory controller supporting such protocols is described.