Interruptible Memory Refresh Segmentation
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Solution Overview
Problem
As processor speeds increase, memory performance becomes a limiting factor due to the need for periodic refreshing of memory devices like DRAM, which renders them inaccessible during refresh periods, leading to increased lockout time and decreased system performance.
Innovation Solution
Implementing an interruptible refresh method that allows memory devices to execute commands simultaneously with segment refreshes, enabling the memory controller to determine the number of segment refreshes to execute and prioritize commands, thereby reducing the delay caused by refreshing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If periodic refresh is performed on DRAM devices, then data loss is prevented, but memory accessibility is reduced and lockout time increases
Solution Approach 1:
The refresh operation is divided into multiple independent segment refreshes instead of a single monolithic refresh. Each segment refresh operates on a different bank or portion of the memory array, allowing other segments to remain accessible during the refresh process. This segmentation enables partial memory accessibility during refresh, reducing the overall lockout time while maintaining data retention.
Solution Approach 2:
The patent implements interruptible periodic refresh where the refresh operation can be paused and resumed based on system needs. The refresh periodicity is maintained to prevent data loss, but the ability to interrupt and delay segment refreshes allows the system to prioritize other operations when necessary, reducing effective lockout time while preserving the periodic refresh requirement for reliability.
2Duration of action of moving object
If memory banks are refreshed simultaneously, then refresh completion is faster, but all memory becomes inaccessible during refresh
Solution Approach 1:
The memory array is divided into multiple banks or segments that can be refreshed independently. Instead of refreshing all banks simultaneously which would cause complete lockout, the system refreshes one segment at a time while allowing access to other segments. This maintains overall refresh functionality while preserving partial memory accessibility during the refresh process.
Solution Approach 2:
The refresh operation is made dynamic and configurable rather than static and fixed. The system can adjust the number of simultaneous segment refreshes, the timing between segments, and the ability to interrupt refresh based on current system demands. This dynamic approach allows optimization between refresh speed and memory accessibility depending on operational priorities.
3Reliability
If refresh command is issued periodically, then data retention is ensured, but system performance is limited by refresh overhead
Solution Approach 1:
By segmenting the refresh operation into multiple independent units, the system can maintain the required periodic refresh for data retention while allowing other memory operations to proceed in parallel on non-refreshed segments. This increases effective system productivity by reducing the proportion of time memory is locked out for refresh operations.
Solution Approach 2:
The patent enables continuous memory access during refresh operations by allowing commands to be issued and executed during segment refresh intervals. The useful action of memory access continues uninterrupted on segments not currently being refreshed, eliminating idle periods and maintaining continuous productivity while still ensuring periodic refresh for data retention.
Data Source
AI summary
A refresh command is received from a memory controller. An interruptible refresh containing multiple segment refreshes is initiated. The segment refreshes are separated by interrupt boundaries. A command is received before execution of a segment refresh. The first command is executed and execution of the first segment refresh is delayed at a first interrupt boundary. Alternatively, a first number of segment refreshes to execute is received from a memory controller. The received first number of segment refreshes is executed. A second number of segment refreshes to execute is received from a memory controller. The received second number of segment refreshes is executed. No segment refreshes are executed between the execution of the first number of segment refreshes and the execution of the second number of segment refreshes.