Interruptible Store Exclusive Atomic Memory Operations
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Solution Overview
Problem
Advanced Microcontroller Bus Architecture (AMBA) systems face challenges in handling interrupts during atomic exclusive memory operations, particularly in high-performance systems, leading to potential deadlocks and unpredictable latencies, which are problematic for real-time operation certification.
Innovation Solution
The introduction of a split STREX primitive into STREX_INIT and STREX_SYNC operations, where STREX_INIT is not interruptible but determinate, and STREX_SYNC is interruptible, allowing for timely handling of interrupts and ensuring atomicity by polling a flag for the return value, ensuring the operation's success or failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional atomic exclusive store operation is used, then atomicity is guaranteed, but interrupt handling is blocked leading to deadlocks and unpredictable latencies
Solution Approach 1:
The atomic store operation is segmented into two distinct phases: STREX_INIT which initiates the exclusive store transaction and sets up the atomicity guarantee, and STREX_SYNC which synchronizes and completes the operation by polling for the return value. This segmentation allows interrupt handling to occur between the two phases without breaking atomicity, resolving the contradiction between guaranteed atomicity and timely interrupt response.
Solution Approach 2:
The STREX_INIT phase performs preliminary actions to establish the exclusive store transaction and prepare the atomicity guarantee before actual completion. By performing this preliminary setup first, the system can then handle interrupts during the synchronization phase without compromising the atomicity that was already established, thus reducing interrupt latency while maintaining reliability.
2Loss of time
If interrupts are allowed during exclusive memory operations, then interrupt latency is reduced, but atomicity may be broken leading to incorrect operations
Solution Approach 1:
The invention introduces an intermediary mechanism in the form of a flag register that tracks the state of the exclusive store operation. The STREX_INIT phase sets this flag to indicate atomicity is established, and STREX_SYNC polls this flag to determine when the operation is complete. This intermediary allows the system to safely handle interrupts in between phases while maintaining atomicity guarantees, as the flag provides a clear state indication that preserves correctness.
3Reliability
If a non-interruptible atomic operation is used, then atomicity is preserved, but system responsiveness to interrupts deteriorates
Solution Approach 1:
By segmenting the atomic operation into STREX_INIT and STREX_SYNC phases, the system can maintain atomicity during the critical initialization phase while allowing interrupt handling during the synchronization phase. This segmentation improves system responsiveness without sacrificing the atomicity guarantee that is established in the first phase.
Solution Approach 2:
The invention makes the atomic operation dynamic by allowing its interruptibility characteristics to change between phases. STREX_INIT is designed to be non-interruptible to ensure atomicity establishment, while STREX_SYNC is designed to be interruptible to improve system responsiveness. This dynamic approach allows the system to adapt its interrupt handling behavior based on the operational phase, thereby improving overall productivity while maintaining reliability.
Data Source
AI summary
In one example, there is disclosed herein a processor configured for interruptible atomic exclusive memory operations. For example, a load exclusive (LDEX) may be followed by a store exclusive (STREX), with the two together forming an atom. To facilitate timely handling of interrupts, the STREX operation is split into two parts. The STREX_INIT is not interruptible but has a determinate execution time because it takes a fixed number of clock cycles. The STREX_INIT sends the value out to the memory bus. It is followed by a STREX_SYNC operation that polls a flag for whether a return value is available. STREX_SYNC is interruptible, and methods are disclosed for determining whether, upon return from an interrupt, atomicity of the operation has been broken. If atomicity is broken, the instruction fails, while if atomicity is preserved, the instruction completes.