Interruptible Write Block for Multi-Cycle Memory Writes
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Solution Overview
Problem
In memory devices like RAMs and CAMs, reducing the number of inputs while performing multi-cycle write operations poses a challenge as interrupting the write operation mid-cycle can result in corrupt data, affecting system throughput.
Innovation Solution
An interruptible write block with an interrupt circuit, comprising secondary and primary registers and an interrupt multiplexer, allows for the interruption of write operations without data corruption by using a control signal to manage data flow across multiple clock cycles, enabling a two-to-one reduction in input pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a multi-cycle write operation is performed to reduce the number of inputs, then the number of input pins is reduced, but interrupting the write operation mid-cycle can result in corrupt data
Solution Approach 1:
The write block is divided into multiple registers (first register, second register, third register) that store data at different stages of the write operation. This segmentation allows the system to capture and preserve data from multiple clock cycles, enabling interruption without data loss while maintaining reduced input pin count.
Solution Approach 2:
The patent introduces an interrupt detection mechanism that acts as an intermediary between the write operation and the memory array. When an interrupt is detected, the system selectively prevents corrupt data from reaching the memory array while preserving valid data in the registers, thus mediating between the multi-cycle write operation and data integrity requirements.
2Productivity
If a multi-cycle write operation is performed, then system throughput is increased by allowing other operations, but interrupting the write operation can result in corrupt data being provided to the memory array
Solution Approach 1:
The system performs preliminary actions by capturing and storing data in multiple registers during the multi-cycle write operation before it is complete. This preliminary storage of data in different registers allows the system to later determine which data is valid and which would be corrupt, enabling safe interruption and resumption of write operations.
Solution Approach 2:
The interrupt detection mechanism provides feedback about the state of the write operation. When an interrupt is detected, the system uses this feedback to selectively prevent corrupt data from being written to the memory array while allowing valid data to proceed, thus maintaining data validity while enabling high throughput operations.
Data Source
AI summary
A disclosed embodiment is an interruptible write block comprising a primary register having an input coupled to an input of the interruptible write block, a secondary register having an input selectably coupled to an output of the primary register and to an output of the secondary register through an interrupt circuit. The interrupt circuit is utilized to interrupt flow of new data from the primary register to the secondary register during an interrupt of a write operation, such that upon resumption of the write operation the secondary register contains valid data. A method of utilizing an interruptible write block during a write operation comprises loading data into a primary register, interrupting the write operation to perform one or more other operations, loading the data into a secondary register while loading new data into the primary register, and resuming the write operation using valid data from the secondary register.