Intersect Area Design Rule for Semiconductor Overlap
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor design methodologies are constrained by complex ground rules that limit design flexibility and often result in over-engineering, leading to increased area usage and potential rule violations, despite meeting performance specifications.
Innovation Solution
A method employing an intersect area calculation between vertically adjoining levels to determine compliance with design rules, incorporating line edge biasing, critical dimension tolerance, and corner rounding, allowing for optimized design data creation that meets performance specifications without overly restrictive ground rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex ground rules with predefined widths and lengths are applied to ensure minimum overlap, then manufacturing yield and reliability are improved, but design flexibility and ease of operation deteriorate
Solution Approach 1:
The patent changes the ground rule from predefined discrete width/length values to a continuous parameter-based approach using intersect area calculations. Designers can now specify overlap requirements as continuous parameters (e.g., minimum intersect area) rather than being constrained to predefined discrete values, thereby maintaining reliability while improving design flexibility.
Solution Approach 2:
Instead of requiring designers to manually adjust shapes to meet complex predefined ground rules, the patent inverts the approach by providing automated tools that calculate intersect areas and generate compliance reports. This inversion shifts the burden from manual designer adjustment to automated system evaluation, freeing designers to focus on higher-level design decisions.
2Reliability
If ground rules are applied to ensure minimum overlap between vertically adjoining levels, then electrical contact reliability is improved, but device complexity and rule complexity increase
Solution Approach 1:
The patent extracts the essential requirement from complex ground rules - the need for sufficient electrical contact - and formulates it as a single clear criterion: minimum intersect area. This extraction simplifies the ground rule from a complex set of logical instructions to a single measurable parameter, making it easier to understand and apply while maintaining electrical contact reliability.
Solution Approach 2:
The intersect area calculation serves multiple functions simultaneously: it evaluates compliance with ground rules, calculates electrical contact metrics, determines overlap sufficiency, and generates design optimization recommendations. This multi-functionality reduces the need for separate complex checking mechanisms, thereby reducing overall system complexity.
3Reliability
If ground rules are set to meet performance criteria in worst combinations, then reliability is improved, but area usage increases due to over-engineering
Solution Approach 1:
The patent enables partial compliance with ground rules by allowing designers to optimize each specific contact interface individually based on actual design needs rather than applying uniform excessive margins throughout. The automated intersect area calculation identifies only the critical interfaces requiring attention, allowing designers to apply sufficient (not excessive) overlap only where needed, thereby reducing overall area usage while maintaining reliability.
Solution Approach 2:
The patent implements feedback mechanisms through automated intersect area calculations that provide real-time compliance status and optimization recommendations. This feedback loop allows designers to adjust their designs iteratively to meet minimum performance requirements without over-engineering, as the system continuously monitors and reports on intersect area compliance, enabling precise optimization of design area.
Data Source
AI summary
A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical dimension tolerance, overlay tolerance, and corner rounding to provide an accurate estimate of a physical area for each of the structures corresponding to the two design elements. The intersect area is employed as a metric to determine compliance with a ground rule, i.e., the ground rule is specified in terms of the intersect region. Other derived quantities such as electrical resistance, electromigration resistance, expected yield may be calculated from the intersect area, and may be advantageously employed to optimize the design data.