Interval Analysis for Out-of-Order Chip Performance Bottlenecks
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Solution Overview
Problem
Conventional performance analysis methods are inadequate for chips with 'out-of-order execution' functionality, as they cannot effectively identify bottlenecks and optimize performance due to the complex timing relationships between tasks.
Innovation Solution
A performance analysis system and method that includes a picker module to capture time information and a calculation circuit to perform interval analysis, calculating the overlap period between tasks and counting the time occupied by unit circuits within the total execution time, allowing for effective processing time evaluation and optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general performance analysis method is used, then analysis simplicity is maintained, but it cannot be applied to chips with out-of-order execution
Solution Approach 1:
The patent segments the performance analysis by introducing task identifiers and dividing the analysis into individual task levels. Each task's time information is captured and analyzed separately, allowing the system to handle out-of-order execution by treating each task as an independent unit that can be tracked through the pipeline stages, thus enabling applicability to out-of-order execution chips while maintaining manageable complexity
Solution Approach 2:
The patent introduces an intermediary data structure (task information including task identifier and time information) that mediates between the complex out-of-order execution operations and the performance analysis. This intermediary layer captures the necessary timing data for each task without requiring direct complex analysis of the out-of-order execution mechanisms themselves, enabling the analysis method to work with out-of-order execution chips
2Productivity
If parallel processing with overlap is implemented, then processing throughput is improved, but time measurement accuracy deteriorates
Solution Approach 1:
The patent segments the time measurement by capturing time information at specific pipeline stages (such as write-back stage) for each individual task. By measuring the time each task spends in the pipeline separately and identifying the overlap period between consecutive tasks, the system can accurately calculate effective processing time even when tasks are executed in parallel with overlap, thus maintaining measurement precision while enabling high throughput parallel processing
Solution Approach 2:
The patent uses feedback by comparing the time information of consecutive tasks to identify overlap periods. The system captures time information from task information, calculates the overlap between current and previous tasks, and uses this feedback to determine the effective processing time occupied by each circuit unit, enabling accurate measurement despite parallel processing with overlap
Data Source
AI summary
A performance analysis system includes a picker module and a calculation circuit. The picker module is placed in the processing device to capture a plurality of pieces of time information of a unit circuit of each of a plurality of tasks in the processing device during total execution time of processing the plurality of tasks. The calculation circuit performs an interval analysis operation on the time information. The interval analysis operation includes: calculating an overlap period between a current task and a previous task; and counting time occupied by the unit circuit during the total execution time of processing the tasks by the processing device according to a relation between the current time interval of the current task corresponding to the unit circuit and the overlap period.