Intervallic Dynamic Start Voltage Sampling in Memory Sub-systems
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Solution Overview
Problem
Current memory sub-systems face inefficiencies in programming operations due to the need for frequent dynamic start voltage (DSV) sampling and program verify operations, which increase programming time, system overhead, and risk of over-programming, leading to reduced endurance of memory cells.
Innovation Solution
Implementing an intervallic DSV operation that samples only a portion of wordlines, identifying a starting voltage level for the entire group, and skipping program verify operations during the programming of the remaining pages, allowing the use of a consistent DSV offset across the wordline group.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If frequent dynamic start voltage sampling and program verify operations are performed, then programming accuracy is improved, but programming time increases
Solution Approach 1:
The patent segments the wordline group into a sampled portion and a remaining portion. DSV sampling and program verify operations are performed only on the sampled portion, while the remaining portion uses the identified DSV offset without additional sampling or verify operations. This segmentation resolves the contradiction by applying verification only where needed while skipping it in other areas.
Solution Approach 2:
The patent applies partial action by performing DSV sampling and program verify operations on only a portion (sampled portion) of the wordlines rather than all wordlines. This partial verification approach maintains sufficient programming accuracy while significantly reducing the time and overhead associated with complete verification of all wordlines.
2Manufacturing precision
If dynamic start voltage sampling is performed on all wordlines, then programming precision is improved, but system overhead increases
Solution Approach 1:
The patent divides the wordline group into a sampled portion subject to DSV sampling and a remaining portion that uses the identified DSV offset without additional sampling. This segmentation reduces system overhead by eliminating redundant sampling and verify operations on the remaining portion while maintaining programming precision through sampling of the representative portion.
3Manufacturing precision
If program verify operations are performed during programming, then programming accuracy is maintained, but memory cell endurance decreases
Solution Approach 1:
The patent segments the programming process into a sampled portion where program verify operations are performed and a remaining portion where they are skipped. This segmentation maintains programming accuracy for the sampled portion while protecting memory cell endurance by reducing the number of verify operations that stress the cells.
Solution Approach 2:
The patent applies partial verification by performing program verify operations only on the sampled portion of wordlines rather than all wordlines. This partial approach maintains sufficient programming accuracy while reducing the harmful effects of repeated verify operations on memory cell endurance.
4Loss of time
If intervallic DSV sampling is implemented on a portion of wordlines, then programming time is reduced, but voltage sampling accuracy may decrease
Solution Approach 1:
The patent applies local quality by selecting a sampled portion of wordlines that is representative of the entire wordline group. The DSV sampling and offset identification performed on this local sampled portion is then applied to the remaining portion, achieving accurate voltage sampling without the time cost of sampling all wordlines.
Solution Approach 2:
The sampled portion serves the remaining portion by providing the DSV offset information needed for programming. The sampled wordlines perform the function of characterizing the voltage requirements for the entire group, allowing the remaining wordlines to be programmed using this information without requiring separate sampling or verification.
Data Source
AI summary
Control logic in a memory device executes a first operation comprising a first set of programming pulses and a first set of program verify operations on a first portion of a first subset of memory cells to be programmed to identify a first start voltage level. A second set of programming pulses including at least one programming pulse having the first start voltage level is caused to be applied to program a second portion of the first subset of memory cells. A second operation including a third set of programming pulses and a second set of program verify operations are executed on a first portion of the second subset of memory cells to identify a second start voltage level.


