Interwound Planar Inductors for High Density Integration
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Solution Overview
Problem
Existing inductor manufacturing techniques, such as deposition and wet-etching, result in wide spacing and low inductance per unit area, and the integration of multiple inductors on semiconductor chips requires significant area, limiting their density and performance.
Innovation Solution
The method involves interwinding inductors on the same planar level and stacking them to create high-density configurations, using deposition, etching, and planarization techniques, allowing for closer coil spacing and increased inductance by forming inductors within each other and connecting them in various configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If deposition and wet-etching techniques are used to manufacture inductors, then the manufacturing process is simple and well-established, but the spacing between inductor windings becomes wide resulting in low inductance per unit area
Solution Approach 1:
The patent applies nesting by forming one inductor structure within another inductor structure. Specifically, a first inductor is formed with windings, then a second inductor is formed within the spaces between the first inductor's windings. This nested configuration allows both inductors to share the same planar space, dramatically increasing the inductance density without requiring additional chip area or complex 3D stacking processes.
Solution Approach 2:
The patent transitions from conventional side-by-side or stacked inductor configurations to a nested configuration where inductors are embedded within each other's winding spaces. This dimensional reorganization allows the inductors to occupy the same planar footprint while maintaining electrical separation, effectively utilizing the negative space between windings to achieve high density without increasing the manufacturing process complexity.
2Quantity of substance
If multiple inductors are fabricated on different layers or on a single layer, then multiple inductor functions are achieved, but a considerable amount of semiconductor chip area is consumed
Solution Approach 1:
The patent forms a second inductor within the winding spaces of a first inductor on the same planar level. This nested arrangement allows two complete inductor structures to coexist within the footprint of a single conventional inductor, effectively doubling the inductor quantity without proportionally increasing the chip area. The technique can be extended to nest additional inductors within remaining spaces.
Solution Approach 2:
The patent merges the spatial occupation of multiple inductors into a single nested structure. By combining the first and second inductors within the same planar footprint and using shared deposition and etching processes, the patent achieves multiple inductor functions while minimizing the total area required on the semiconductor chip.
3Manufacturing precision
If inductors are interwound on the same planar level, then high density and high inductance are achieved, but electrically separating the interwound inductors becomes difficult
Solution Approach 1:
The patent extracts the electrical connection paths of the nested inductors to separate terminals. By providing distinct access points for each inductor's start and end points, the patent enables electrical separation and independent connection of the nested inductors. This extraction of connection paths allows the inductors to be electrically isolated while maintaining their nested physical configuration, resolving the difficulty of separating electrically interwound structures.
Solution Approach 2:
The patent uses an insulating layer as an intermediary between the nested inductor windings. This insulating barrier prevents electrical shorting between the first and second inductors while allowing them to be closely spaced for maximum density. The intermediary insulating material enables the inductors to be formed using standard deposition and etching techniques without requiring complex electrical isolation structures.
Data Source
AI summary
There is provided a method of making two electrically separated inductors using deposition and wet-etching techniques, which inductors are formed by interwinding one of the inductors within the other inductor on the same planar level. In still another aspect of the invention, there is provided a method of making various levels inductors, each level having at least two electrically separated inductors, using deposition and wet-etching techniques. The inductors on each planar level are formed by interwinding one of the inductors within the other inductor, and then stacking these in a preferred manner. In still another aspect, there is provided a manner of connecting together inductors formed according to the above methods in order to achieve various inductor configurations.