In-Tier Driver Circuit for Memory Tiers
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Solution Overview
Problem
The challenge in memory devices is the inefficiency and scalability issues due to the poor conductivity and cutoff performance of transistors in driver circuits, particularly as the number of tiers increases, leading to limitations in memory array efficiency and difficulty in accommodating higher memory cell density.
Innovation Solution
The implementation of an in-tier driver circuit where transistors are embedded within the tiers, allowing for shared gates among transistors from the same and different tiers, connected in series and parallel, and utilizing a graded biasing technique to improve voltage distribution, thereby enhancing drive capability and reducing wire routing and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If transistors are located in a separate structure from the substrate, then driver circuit functionality is achieved, but memory array efficiency deteriorates and scalability is limited
Solution Approach 1:
The driver circuit transistors are merged with the memory cell tiers, forming an integrated structure where driver transistors and memory cells coexist on the same substrate without separate structures. This integration eliminates the limitations of separate structures while maintaining driver circuit functionality and improving memory array efficiency.
Solution Approach 2:
The driver circuit is implemented by utilizing the vertical stacking dimension, where driver transistors are formed in association with multiple tiers stacked vertically. This allows the driver circuit to accommodate increased memory cell density through tier stacking without requiring additional lateral space or separate structures.
2Quantity of substance
If the number of tiers increases to achieve higher memory cell density, then memory capacity is improved, but driver circuit scalability deteriorates due to poor transistor conductivity
Solution Approach 1:
The driver circuit is segmented into multiple transistor groups, where each group is associated with a specific tier or set of tiers. This segmentation allows independent optimization of each transistor group's conductivity and performance, enabling the driver circuit to scale effectively as the number of tiers increases.
Solution Approach 2:
Different transistor groups are optimized with local quality variations, where transistors associated with different tiers have tailored characteristics to meet specific conductivity requirements. This allows each region of the driver circuit to be optimized for its specific function and tier association, improving overall scalability.
3Ease of manufacture
If conventional transistor structures are used, then manufacturing simplicity is maintained, but conductivity and cutoff performance deteriorate
Solution Approach 1:
The transistor structure parameters are changed by forming transistors with specific dimensional ratios, where the channel width-to-length ratio is optimized to achieve both high conductivity and good cutoff performance. These parameter changes are achieved through standard manufacturing processes, maintaining ease of manufacture while improving reliability.
Data Source
AI summary
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, each of the tiers including memory cells and a control gate for the memory cells, each of the tiers including first transistors connected in series between the control gate in a respective tier and a conductive line, and second transistors connected in series between the control gate in the respective tier and the conductive line, the second transistors connected in parallel with the first transistors between the control gate and the conductive line, conductive joints coupled to channel regions of the first and second transistors, and gates for the first transistors and second transistors, each of the gates shared by one of the first transistors and one of the second transistors.