Intra-block Copy Decoding Dynamic Memory Remapping
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Solution Overview
Problem
Existing video decoding technologies face challenges in efficiently accessing large amounts of previously decoded pixels during intra-block copy (IBC) decoding, leading to high costs in terms of area, power consumption, and access latency.
Innovation Solution
The implementation of a dynamic remapping technique that maps virtual addresses used in IBC decoding to smaller on-chip memory addresses, allowing for efficient access to reconstructed blocks without the need for large on-chip SRAM or off-chip storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If on-chip SRAM storage is used to store previously decoded pixels for IBC decoding, then access speed is improved, but chip area increases prohibitively
Solution Approach 1:
The patent implements dynamic remapping of virtual memory addresses to physical on-chip memory addresses. The system dynamically adjusts the mapping between the virtual address space (which provides fast access) and the physical on-chip memory (which provides fast access), allowing the same small on-chip memory to serve the function of a large virtual memory buffer by dynamically reconfiguring the address mapping based on decoding progress and access patterns.
Solution Approach 2:
The patent introduces a virtual memory layer as an additional dimension between the processor and physical memory. By mapping virtual addresses to physical on-chip memory addresses dynamically, the system creates a layered memory hierarchy that provides both fast on-chip access and the functionality of large buffer storage, resolving the area-speed tradeoff.
2Area of stationary object
If off-chip DRAM storage with cached-DMA is used to store previously decoded pixels, then chip area is reduced, but power consumption increases and access latency increases
Solution Approach 1:
The patent introduces dynamic address remapping as an intermediary mechanism between the virtual memory buffer and physical on-chip memory. This intermediary layer allows the system to maintain fast on-chip access while using a compact on-chip buffer, eliminating the need for off-chip DRAM and its associated power consumption and latency issues.
3Area of stationary object
If off-chip DRAM storage with cached-DMA is used to store previously decoded pixels, then chip area is reduced, but access latency increases
Solution Approach 1:
The dynamic address remapping mechanism serves as an intermediary that bridges virtual memory addressing with physical on-chip memory access. This allows the system to maintain small on-chip buffer area while achieving fast access by dynamically mapping addresses, thereby eliminating the latency penalty of off-chip DRAM access.
Data Source
AI summary
A device includes a decoder configured to identify, during an intra-block copy (IBC) decoding process on at least a portion of a coding unit of video data, a target virtual address in a virtual address space associated with a read operation of the IBC decoding process. The target virtual address is generated according to an addressing scheme of an on-chip memory used by the IBC decoding process. The decoder is configured to identify, based on the target virtual address, an on-chip memory start address of a portion of the on-chip memory. The on-chip memory is configured to store reconstructed blocks of the video data. The decoder is also configured to perform the read operation to read a block of pixel data from the on-chip memory using the on-chip memory start address.