Intra-Core Lockstep Error Recovery in Processing Pipelines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current data processing systems face challenges in efficiently detecting and correcting errors caused by hardware faults, such as bit flips and permanent defects, especially in safety-critical applications like automotive systems, where existing fault tolerance methods often require significant resource duplication or software redundancy, leading to performance delays and loss of progress.
Innovation Solution
The implementation of an intra-core lockstep mode in a processing pipeline, where redundant operations are performed alongside main processing, with error handling circuitry that detects mismatches between main and checker operations to trigger recovery operations, allowing for error correction without aborting the main processing and preserving previous progress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional fault tolerance methods are used with significant resource duplication, then error detection coverage is improved, but resource overhead and device complexity increase
Solution Approach 1:
The patent merges the main processing and checker processing into a single processing pipeline, sharing common hardware resources such as the execute stage, front end stages, and supporting structures. This consolidation reduces device complexity and resource overhead while maintaining error detection coverage through the lockstep execution model where checker operations verify main operations.
2Reliability
If traditional fault tolerance methods abort main processing on error detection, then reliability is improved, but loss of time and productivity worsen
Solution Approach 1:
The patent performs checker operations in parallel with main operations during the same clock cycles, completing verification before the main processing commits results. This preliminary checking allows the system to detect errors without aborting main processing, as the checker has already verified the correctness of operations before they are finalized.
Solution Approach 2:
The patent implements a feedback mechanism where checker operation results are compared with main operation results, and mismatch detection triggers selective recovery operations. This feedback loop enables continuous verification without interrupting the main processing flow, as corrections are applied only when errors are detected through the comparison feedback.
3Reliability
If redundant checker processing is added to the pipeline, then error detection capability is improved, but device complexity and resource usage increase
Solution Approach 1:
The patent makes the processing pipeline multi-functional by enabling it to perform both main processing and checker processing using the same execute stage and front end stages. The pipeline is configured to execute main operations and corresponding checker operations sequentially within the same hardware resources, reducing device complexity while maintaining error detection capability.
Solution Approach 2:
The patent implements periodic verification where checker operations are inserted at regular intervals to verify main processing results. The lockstep execution model periodically compares main operation results with checker operation results, enabling error detection without requiring continuous dedicated checker resources, thus reducing overall pipeline complexity.
Data Source
AI summary
An apparatus has a processing pipeline (2) comprising an execute stage (30) and at least one front end stage (10), (20), (25) for controlling which micro operations are issued to the execute stage. The pipeline has an intra-core lockstep mode of operation in which the at least one front end stage (10), (20), (25) issues micro operations for controlling the execute stage (30) to perform main processing and checker processing. The checker processing comprises redundant operations corresponding to associated main operations of at least part of the main processing. Error handling circuitry (200), (210) is responsive to the detection of a mismatch between information associated with given checker and main operations to trigger a recovery operation to correct an error and continue forward progress of the main processing.