Intra-die Yield Prediction via Tile Partitioning and Variation Modeling
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Solution Overview
Problem
Conventional methods for predicting integrated circuit manufacturing yield fail to account for systematic and random intra-die variations, leading to increased manufacturing costs due to reduced yield, as they do not consider the physical layout of the chip and spatial correlations of random variations.
Innovation Solution
A system that predicts manufacturing yield by partitioning a die into tiles, computing systematic and random variations, and accounting for spatial correlations between tiles, using a covariance matrix and perfect-correlation windows to reduce computational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional yield prediction methods are used that do not consider physical layout, then the prediction method is simple, but manufacturing yield prediction accuracy deteriorates due to ignoring intra-die variations
Solution Approach 1:
The die is partitioned into an array of tiles, where each tile represents a local region for computing systematic variations. This segmentation allows the model to capture layout-dependent intra-die variations at a manageable granularity, improving yield prediction accuracy without requiring full-chip complexity for each calculation
Solution Approach 2:
The patent applies different variation characteristics to different regions of the die by computing systematic variations for each tile based on its specific layout. This local quality approach allows the model to account for spatially varying process parameters while maintaining computational efficiency through region-based aggregation
2Measurement precision
If full-chip simulation tools are used to evaluate systematic intra-die variations, then yield prediction accuracy improves, but computational complexity increases significantly
Solution Approach 1:
By dividing the die into tiles and computing systematic variations independently for each tile, the patent reduces computational complexity from full-chip simulation to manageable tile-level calculations, while still capturing the essential layout-dependent variations
Solution Approach 2:
The patent combines tile-level systematic variation computations with random variation models to create a comprehensive yield prediction model. This merging allows efficient computation at the tile level to be aggregated into accurate full-die yield predictions without requiring resource-intensive full-chip simulations
3Measurement precision
If spatial correlations of random variations are not considered, then the prediction model is simpler, but manufacturing yield prediction accuracy deteriorates due to ignoring intra-die location correlations
Solution Approach 1:
The patent incorporates spatial correlations by considering the relationship between random variations at different intra-die locations. This local quality approach models the correlation structure specific to each region while maintaining overall model efficiency through the tile-based framework
Data Source
AI summary
One embodiment of the present invention provides a system that predicts manufacturing yield for a die within a semiconductor wafer. During operation, the system first receives a physical layout of the die. Next, the system partitions the die into an array of tiles. The system then computes systematic variations for a quality indicative value to describe a process parameter across the array of tiles based on the physical layout of the die. Next, the system applies a random variation for the quality indicative parameter to each tile in the array of tiles. Finally, the system obtains the manufacturing yield for the die based on both the systematic variations and the random variations.