Intra Prediction Processor Block Partitioning Cost Optimization
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Solution Overview
Problem
High Efficiency Video Coding (HEVC) requires an efficient algorithm for block partitioning to balance prediction accuracy and bit rate, as smaller block sizes provide better predictions but are more expensive to code due to increased overhead.
Innovation Solution
A hardware processor performs intra mode searches for different block sizes, computes cost values using simplified distortion and bit rate estimates, and selectively merges blocks to determine the final partition, refining intra modes based on these calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If smaller block sizes are used for intra prediction, then prediction accuracy is improved, but coding cost increases due to increased overhead
Solution Approach 1:
The patent divides the block partitioning process into multiple stages: initial partitioning into candidate blocks, cost computation for each candidate size, and selective merging based on cost values. This segmentation allows the system to evaluate different block sizes systematically and merge blocks when it reduces overall coding cost, thereby resolving the contradiction between using small blocks for accuracy and large blocks for reduced overhead.
Solution Approach 2:
The patent implements dynamic block size selection by computing cost values for different block sizes and selectively merging blocks based on these costs. The block partitioning is not fixed but adapts dynamically based on the computed costs, allowing the system to choose the optimal block size for each region, balancing prediction accuracy and coding cost.
2Measurement precision
If full intra mode search is performed for all block sizes, then best intra mode selection is achieved, but computational complexity increases
Solution Approach 1:
The patent performs preliminary cost computation for different block sizes before finalizing the partitioning. By computing simplified distortion estimates and bit rate estimates in advance, the system identifies promising block sizes and intra modes early, reducing the need for exhaustive searches later and thereby lowering computational complexity while maintaining accuracy.
Solution Approach 2:
The patent uses simplified distortion estimates and bit rate estimates as approximations during the block partitioning process. These simplified cost computations serve as disposable, low-cost evaluations that guide the partitioning decisions without requiring full, computationally expensive intra mode searches for all candidates, thus reducing overall computational complexity.
3Measurement precision
If more blocks are created through partitioning, then prediction precision is improved, but bit rate increases due to overhead
Solution Approach 1:
The patent implements a block merging process where candidate blocks of the same size are evaluated based on computed cost values. Blocks with similar characteristics and low merging costs are combined into larger blocks, reducing the total number of blocks and thereby reducing the bit rate overhead while maintaining prediction precision through the selective merging of compatible blocks.
Solution Approach 2:
The patent changes the block size parameter dynamically based on computed costs. By adjusting block sizes according to the balance between prediction precision and bit rate overhead, the system optimizes the partitioning structure to achieve high prediction accuracy without excessive bit rate increase from too many small blocks.
Data Source
AI summary
A hardware processor has a per block size intra mode processor to perform intra mode searches for best intra modes for different block sizes. A cost processor computes cost values for the different block sizes, where the cost values are based upon at least one of a simplified distortion estimate or a simplified bit rate estimate. A selective block merger processor establishes a final partition of blocks.