Intra Prediction Processing Order Inversion for Parallel Encoding

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Solution Overview

Problem

Current image encoding methods lack efficiency in accelerating encoding processes, particularly in intra prediction, due to limitations in processing order and parallel processing capabilities.

Innovation Solution

The method involves dividing coding unit blocks into processing blocks for intra prediction, selecting intra prediction modes, and modifying the processing order to prohibit lower-left reference modes, allowing parallel processing and rearranging quantization coefficients to conform to the HEVC standard.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If intra prediction is performed in the conventional processing order (first processing block then second processing block), then the encoding process follows the standard bitstream writing order, but parallel processing cannot be performed and encoding speed is limited

Engineering Contradiction:
Improveencoding speedVSAvoidprocessing order complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent inverts the conventional processing order by performing intra prediction on the second processing block (upper right) before the first processing block (lower left), despite the bitstream writing order requiring the opposite sequence. This inversion enables parallel processing acceleration while maintaining standard compliance through subsequent coefficient rearrangement.

Inventive Principle:
Principle #13The other way round (Inversion)

2Productivity

If lower-left reference mode is permitted for the second processing block, then more prediction modes are available, but processing dependency prevents parallel execution

Engineering Contradiction:
Improveparallel processing capabilityVSAvoidprediction mode flexibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent extracts the lower-left reference mode from the available prediction modes for the second processing block, prohibiting its use to eliminate processing dependency. This allows the second block to be processed independently in parallel, while the removed mode's functionality is effectively handled through alternative prediction modes and subsequent coefficient rearrangement.

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If processing order is modified to enable parallel processing, then encoding is accelerated, but compliance with the predetermined coding standard may be compromised

Engineering Contradiction:
Improveencoding speedVSAvoidstandard compliance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent segments the encoding process into two independent phases: (1) parallel intra prediction processing on processing blocks, and (2) rearrangement of quantization coefficients to match the standard bitstream order. This segmentation allows speed optimization in the first phase while ensuring standard compliance in the second phase.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses quantization coefficients as an intermediary between the parallel processing order and the standard bitstream writing order. By rearranging these coefficients after parallel processing, the system mediates between the optimized processing sequence and the required standard compliance, ensuring both speed and reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10038901B2Image encoding method and image encoding apparatus
Publication Date: 2018.07.31 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO LTD
  • US10038901B2 patent drawing
  • US10038901B2 patent drawing
  • US10038901B2 patent drawing

AI summary

An image encoding method includes: selecting, for each processing block, one of intra prediction modes specified by a coding standard, and performing intra prediction according to the intra prediction mode, wherein the intra prediction modes include a lower-left reference mode in which a processing block located at lower left of a current processing block is referred to, the processing blocks include a first processing block and a second processing block located at upper right of the first processing block, the second processing block being equal in size to the first processing block, the coding standard defines that information on the second processing block is written into a bitstream after information on the first processing block.