Intra-Stack Encapsulation for IC Warpage Mitigation

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Solution Overview

Problem

Integrated circuit density is limited by warpage issues in stacked packages, leading to poor yields, device failures, and increased costs due to compromised mechanical and electrical connectivity, especially under harsh environmental conditions.

Innovation Solution

A stacked integrated circuit package system with an intra-stack encapsulation between carriers, which surrounds intra-stack interconnects and provides structural rigidity, mitigating warpage and eliminating the need for additional protective covers or interposers, thus maintaining a low profile and improving reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple integrated circuits are stacked in a compact package to increase density, then integrated circuit density is improved, but warpage occurs compromising mechanical properties and electrical connectivity

Engineering Contradiction:
Improveintegrated circuit densityVSAvoidmechanical properties and electrical connectivity
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

An underfill encapsulant material is introduced as an intermediary substance between the integrated circuit stack and the bottom package carrier. This encapsulant fills the gap and surrounds the interconnects, acting as a mediator that distributes mechanical stress and prevents warpage while maintaining electrical connectivity. The encapsulant material specifically targets the warpage problem by providing structural support without compromising the compact stacked design.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Strength

If the bottom assembly is made more robust to prevent warpage, then mechanical strength is improved, but manufacturing complexity and cost increase

Engineering Contradiction:
Improvemechanical strengthVSAvoidmanufacturing complexity
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The mechanical properties of the package structure are improved by changing the parameters of the encapsulant material rather than redesigning the entire bottom assembly. By selecting encapsulant materials with appropriate viscosity, curing characteristics, and mechanical properties, the system achieves enhanced warpage resistance without increasing manufacturing complexity. The process integrates seamlessly with existing underfill techniques.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If underfill encapsulant material is applied to protect connections, then reliability is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveelectrical connectivityVSAvoidencapsulant application precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The encapsulant material is applied in a manner that allows it to self-distribute and self-level within the gap between the IC stack and carrier. The material's rheological properties enable it to automatically fill voids and conform to the underlying structure without requiring high-precision alignment or complex application equipment. This self-service characteristic reduces manufacturing precision requirements while ensuring complete coverage of interconnects.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS7871861B2Stacked integrated circuit package system with intra-stack encapsulation
Publication Date: 2011.01.18 STATS CHIPPAC MANAGEMENT PTE LTD
  • US7871861B2 patent drawing
  • US7871861B2 patent drawing
  • US7871861B2 patent drawing

AI summary

A stacked integrated circuit package system includes: mounting a first integrated circuit over a first carrier; mounting a second integrated circuit package system having a second carrier with an intra-stack interconnect attached thereto and with the intra-stack interconnect over the first carrier and the first integrated circuit; and forming an intra-stack encapsulation between the first carrier and the second carrier surrounding the intra-stack interconnect.