Intra-die Variation Measurement Using Bounded Test Macros
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Solution Overview
Problem
Integrated circuit designs face challenges in accurately determining intra-die variation (ACV) and region of influence (ROI) effects, which affect the performance and consistency of transistors and circuits on a microchip, due to manufacturing variations and environmental influences.
Innovation Solution
The method involves using a test macro with multiple test structures, each containing identical performance monitors surrounded by unique bounding circuitry, positioned close together to minimize systematic ACV and distinguish between ACV and ROI effects, allowing for precise characterization of electrical performance deviations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If test structures are positioned far apart on the chip, then systematic ACV between test structures is reduced, but the ability to distinguish ACV from ROI effects deteriorates
Solution Approach 1:
The patent applies local quality by creating test structures with identical performance monitors surrounded by unique bounding circuitry. Each test structure is locally differentiated by its bounding circuitry while maintaining identical core monitors, allowing the measurement to capture ACV effects specific to each local region while controlling for ROI effects through the standardized monitor design.
Solution Approach 2:
The patent segments the chip into multiple test structures, each containing identical performance monitors but with different bounding circuitry. This segmentation allows independent measurement of ACV within each segment while the repeated monitor designs enable statistical separation of ACV from ROI effects through comparative analysis.
2Stability of the object's composition
If identical performance monitors are used in all test structures, then ACV measurement consistency is improved, but the ability to characterize local environmental effects deteriorates
Solution Approach 1:
The patent uses identical performance monitors (maintaining consistency) while varying the bounding circuitry surrounding each monitor (introducing local quality). This allows the same measurement mechanism to capture different local environmental effects through the unique bounding circuitry configurations in each test structure.
Solution Approach 2:
The patent creates multiple copies of identical performance monitors across different test structures. These copies serve as standardized measurement references that can be statistically compared to distinguish ACV from ROI effects, while each copy is embedded in unique bounding circuitry that characterizes local environmental conditions.
3Manufacturing precision
If test structures are positioned close together, then systematic ACV between test structures is minimized, but measurement precision for distinguishing ACV from ROI effects deteriorates
Solution Approach 1:
The patent divides the chip into spatially separated test structures, each with identical performance monitors and unique bounding circuitry. This segmentation allows statistical analysis to distinguish ACV from ROI effects by comparing monitors across different locations, while the standardized design ensures measurement precision is maintained despite spatial separation.
Data Source
AI summary
Embodiments of the present invention disclose an apparatus and method to determine the intra-chip variation of an integrated circuit. In an embodiment, an apparatus comprises a test macro that includes two or more test structures; wherein each test structure includes identical copies of the same performance monitor; wherein each performance monitor has a unique bounding circuitry that encompasses the performance monitor; and wherein the two or more test structures are positioned close enough to each other as to reduce systematic across chip variation between the two or more test structures.