Intrinsic MOSFET Cascode Current Mirror for Low-Headroom Biasing
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Solution Overview
Problem
Nanometer-scale transistor technologies result in low breakdown voltages and reduced output resistances, leading to performance degradation in current mirrors and limiting their operation with low headroom voltage and high output impedance requirements.
Innovation Solution
A cascode current mirror design featuring a common-source composite transistor in series with a first common-gate intrinsic transistor, and a common-source transistor in series with a second common-gate intrinsic transistor, where the gates of the intrinsic transistors are biased at an intermediate node, allowing for reduced headroom voltage and increased output impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If nanometer scale transistor technologies are used, then device scaling and integration density are improved, but output resistance decreases and breakdown voltage reduces
Solution Approach 1:
The current mirror circuit is divided into multiple transistor stages (input transistor, cascode transistors, and composite transistors) to achieve high output impedance while using scaled transistors. The segmentation of the output path into series-connected transistors allows each device to operate in saturation, maintaining high overall output resistance despite individual transistor short-channel effects.
Solution Approach 2:
The patent transitions from a simple single-transistor current mirror to a multi-dimensional cascode structure with series and parallel transistor arrangements. This dimensional expansion in circuit topology allows simultaneous achievement of high output impedance, low headroom voltage, and compatibility with scaled transistor technologies.
2Device complexity
If conventional current mirror structures are used, then circuit simplicity is maintained, but headroom voltage increases and dynamic range is limited
Solution Approach 1:
The circuit employs dynamic voltage distribution across multiple transistor stages, where the cascode transistors dynamically adjust voltage drops to maintain saturation operation. This dynamic operation allows the current mirror to function with reduced static headroom voltage while preserving signal dynamic range.
Solution Approach 2:
Intrinsic transistors are introduced as intermediary elements between the input and output transistors. These intermediate devices serve as voltage buffers that reduce the headroom requirement while maintaining current mirroring accuracy, effectively mediating between the simple current mirror concept and the need for low voltage operation.
3Productivity
If transistor output resistance is low due to short-channel effects, then device scaling is achieved, but current mirror accuracy deteriorates
Solution Approach 1:
The output impedance path is segmented into multiple high-impedance transistor stages connected in series. Each transistor in the cascode stack contributes to the overall output impedance, and their combined effect compensates for the low individual transistor output resistance caused by short-channel effects, thereby maintaining current mirror accuracy.
Solution Approach 2:
The patent uses composite transistor structures (combining intrinsic and regular transistors in series) to create an equivalent device with superior output characteristics. This composite approach allows the current mirror to achieve high output impedance and accurate current copying while utilizing scaled transistors with inherently lower output resistance.
Data Source
AI summary
Methods and devices for a wide-swing cascode current mirror with low headroom voltage and high output impedance are presented. An input leg of the current mirror includes a composite transistor in series connection with an intrinsic transistor. The composite transistor includes two series-connected regular transistors with respective sizes that are twice the size of the intrinsic transistor. An output leg of the current mirror includes a regular transistor in series connection with an intrinsic transistor. A gate voltage of the composite transistor, provided at a node that is common to gates of the two series-connected regular transistors, self-establishes when a reference current flows through the input leg. The self-established gate voltage is used to bias the regular transistor of the output leg. Biasing voltages to gates of the intrinsic transistors is provided by an intermediate node that provides the series connection of the regular transistors of the composite transistor.