Invariant Sharing for Formal Verification Speed

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Solution Overview

Problem

Formal verification systems often struggle to efficiently prove or disprove large and complex circuit designs, leading to performance issues in ensuring the correctness of integrated circuits.

Innovation Solution

The method involves sharing inductive invariants between formal verification engines to speed up the verification process by treating determined inductive invariants as assumptions for other properties, allowing for parallel processing and iterative resource optimization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If formal verification systems prove multiple properties independently for large and complex circuit designs, then each property can be thoroughly verified, but the verification process becomes extremely time-consuming and resource-intensive

Engineering Contradiction:
Improveverification correctnessVSAvoidverification time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary action by determining inductive invariants for certain properties before using them as assumptions in proving other properties. This preliminary determination of inductive invariants reduces the search space for subsequent property proofs, thereby decreasing verification time while maintaining thoroughness.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes parameters by transforming the verification problem into a different parameter space where inductive invariants serve as fixed assumptions. This parameter transformation allows the verification engine to work with reduced complexity for subsequent properties, balancing thorough verification with acceptable time consumption.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If formal verification systems use comprehensive search methods to prove properties, then verification accuracy is maintained, but the computational resources and time required increase significantly

Engineering Contradiction:
Improveverification accuracyVSAvoidverification efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

By determining inductive invariants in advance and using them as assumptions, the system performs preliminary action that reduces the search space for subsequent property proofs. This maintains verification accuracy by using mathematically sound inductive invariants while improving productivity through reduced computational effort.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Inductive invariants serve as intermediaries between the circuit model and the properties to be proven. These intermediaries capture essential behavioral characteristics that can be used as assumptions, thereby reducing the complexity of property proofs while maintaining verification accuracy through the mathematical properties of inductive invariants.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If formal verification systems prove all properties using the same verification engine sequentially, then resource management is simple, but the overall verification process becomes slower

Engineering Contradiction:
Improvesystem complexityVSAvoidverification throughput
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The system determines inductive invariants in advance as preliminary action, which can then be shared across multiple verification engines. This approach enables parallel processing of multiple properties without requiring complex inter-engine communication, maintaining simple resource management while improving verification throughput through concurrent execution.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10325054B2Invariant sharing to speed up formal verification
Publication Date: 2019.06.18 SYNOPSYS INC
  • US10325054B2 patent drawing
  • US10325054B2 patent drawing

AI summary

Methods and apparatuses are described for sharing inductive invariants while performing formal verification of a circuit design. Specifically, some embodiments assume at least an inductive invariant for a property to be true while proving another property. According to one definition, an inductive invariant of a property is an inductive assertion such that all states that satisfy the inductive assertion also satisfy the property. According to one definition, an inductive assertion describes a set of states that includes all legal initial states of the circuit design and that is closed under a transition relation that models the circuit design.